colibri-imx6ull: add initial

The resulting U-Boot boots at least from serial downloader mode.

Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

5 files changed, 176 insertions, 3 deletions

diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig
index bbeec37e9f..d5e6c83031 100644
--- a/arch/arm/cpu/armv7/mx6/Kconfig
+++ b/arch/arm/cpu/armv7/mx6/Kconfig
@@ -79,6 +79,12 @@ config TARGET_COLIBRI_IMX6
 	select DM_SERIAL
 	select DM_THERMAL
 
+config TARGET_COLIBRI_IMX6ULL
+	bool "Toradex Colibri iMX6ULL"
+	select MX6ULL
+	select DM
+	select DM_THERMAL
+
 config TARGET_EMBESTMX6BOARDS
 	bool "embestmx6boards"
 
@@ -268,6 +274,7 @@ source "board/tbs/tbs2910/Kconfig"
 source "board/tqc/tqma6/Kconfig"
 source "board/toradex/apalis_imx6/Kconfig"
 source "board/toradex/colibri_imx6/Kconfig"
+source "board/toradex/colibri-imx6ull/Kconfig"
 source "board/udoo/Kconfig"
 source "board/wandboard/Kconfig"
 source "board/warp/Kconfig"
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index b698421284..69bee95b82 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -284,6 +284,7 @@ dtb-$(CONFIG_VF610) += vf500-colibri.dtb \
 	bk4r1.dtb
 
 dtb-$(CONFIG_MX6) += imx6ull-14x14-evk.dtb \
+	imx6ull-colibri.dtb \
 	imx6dl-icore.dtb \
 	imx6q-icore.dtb
 
diff --git a/arch/arm/dts/imx6ull-colibri.dts b/arch/arm/dts/imx6ull-colibri.dts
new file mode 100644
index 0000000000..28b7ef67ba
--- /dev/null
+++ b/arch/arm/dts/imx6ull-colibri.dts
@@ -0,0 +1,135 @@
+/*
+ * Copyright 2017 Toradex AG
+ *
+ * SPDX-License-Identifier:     GPL-2.0+ or X11
+ */
+
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include "imx6ull.dtsi"
+
+/ {
+	model = "Toradex Colibri iMX6ULL";
+	compatible = "toradex,imx6ull-colibri", "fsl,imx6ull";
+
+	chosen {
+		stdout-path = &uart1;
+	};
+
+	regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		reg_sd1_vmmc: regulator@1 {
+			compatible = "regulator-gpio";
+			regulator-name = "V3.3_1.8_SD";
+			gpio = <&gpio5 9 GPIO_ACTIVE_HIGH>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_reg_sd>;
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <3300000>;
+			states = <1800000 0x1 3300000 0x0>;
+		};
+
+		reg_soc_in: regulator-gpio {
+			compatible = "regulator-fixed";
+			regulator-min-microvolt = <1275000>;
+			regulator-max-microvolt = <1275000>;
+			regulator-name = "gpio_soc_in";
+			regulator-type = "voltage";
+		};
+	};
+
+};
+
+&cpu0 {
+	arm-supply = <&reg_arm>;
+	soc-supply = <&reg_soc>;
+	dc-supply = <&reg_soc_in>;
+};
+
+#if TODO
+&clks {
+	assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
+	assigned-clock-rates = <786432000>;
+};
+#endif
+/* TODO, remove this in U-Boot */
+&i2c1 {
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c1>;
+	pinctrl-1 = <&pinctrl_i2c1_gpio>;
+	sda-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;
+	scl-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>;
+	status = "okay";
+};
+
+&i2c2 {
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c2>;
+	pinctrl-1 = <&pinctrl_i2c2_gpio>;
+	sda-gpios = <&gpio1 31 GPIO_ACTIVE_LOW>;
+	scl-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
+	status = "okay";
+	ad7879@2c {
+		compatible = "todo";
+		reg = <0x2c>;
+	};
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1>;
+	uart-has-rtscts;
+	fsl,dte-mode;
+	status = "okay";
+};
+
+&iomuxc {
+	pinctrl_i2c1: i2c1grp {
+		fsl,pins = <
+			MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
+			MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
+		>;
+	};
+
+	pinctrl_i2c1_gpio: i2c1-gpio-grp {
+		fsl,pins = <
+			MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x4001b8b0
+			MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x4001b8b0
+		>;
+	};
+
+	pinctrl_i2c2: i2c2grp {
+		fsl,pins = <
+			MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
+			MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
+		>;
+	};
+
+	pinctrl_i2c2_gpio: i2c2grp {
+		fsl,pins = <
+			MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x4001b8b0
+			MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x4001b8b0
+		>;
+	};
+
+	pinctrl_reg_sd: reg-sd-grp {
+		fsl,pins = <
+			MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x4001b8b0
+		>;
+	};
+
+	pinctrl_uart1: uart1-grp {
+		fsl,pins = <
+			MX6UL_PAD_UART1_TX_DATA__UART1_DTE_RX	0x79
+			MX6UL_PAD_UART1_RX_DATA__UART1_DTE_TX	0x79
+			MX6UL_PAD_UART1_RTS_B__UART1_DTE_CTS	0x79
+			MX6UL_PAD_UART1_CTS_B__UART1_DTE_RTS	0x79
+		>;
+	};
+};
+
+&iomuxc_snvs {
+};
diff --git a/arch/arm/dts/imx6ull.dtsi b/arch/arm/dts/imx6ull.dtsi
index 65950e8019..b3c5f980b9 100644
--- a/arch/arm/dts/imx6ull.dtsi
+++ b/arch/arm/dts/imx6ull.dtsi
@@ -8,6 +8,7 @@
 
 #include <dt-bindings/clock/imx6ul-clock.h>
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/linux-event-codes.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include "imx6ull-pinfunc.h"
 #include "imx6ull-pinfunc-snvs.h"
diff --git a/arch/arm/imx-common/cmd_writebcb_mx7.c b/arch/arm/imx-common/cmd_writebcb_mx7.c
index 9174a03d14..6dfe7a22e7 100644
--- a/arch/arm/imx-common/cmd_writebcb_mx7.c
+++ b/arch/arm/imx-common/cmd_writebcb_mx7.c
@@ -24,10 +24,22 @@
 #include <linux/bch.h>
 #include <malloc.h>
 #include <nand.h>
+
+#ifdef CONFIG_MX7
+/*
+ * compare with v5_rom_mtd_commit_structures vs. v6_rom_mtd_commit_structures
+ * in imx-kobs/src/mtd.c
+ */
+#define USE_RANDOMIZER
+#define USE_62_BIT_ECC
+#endif
+
+#ifdef USE_RANDOMIZER
 #include "rand.h"
+#define RAND_16K		(16 * 1024)
+#endif
 
 #define PAGES_PER_STRIDE	64
-#define RAND_16K		(16 * 1024)
 
 #define BOOT_SEARCH_COUNT	2 /* match with BOOT_CFG_FUSES [6:5] */
 
@@ -197,6 +209,7 @@ int encode_bch_ecc(void *source_block, size_t source_size, void *target_block,
 	/* gf: FCB_GF */
 	int m, b0, e0, bn, en, n, gf;
 
+#ifdef USE_62_BIT_ECC
 	/* 62 bit BCH, for i.MX6SX and i.MX7D */
 	m = 32;
 	b0 = 128;
@@ -205,6 +218,16 @@ int encode_bch_ecc(void *source_block, size_t source_size, void *target_block,
 	en = 62;
 	n = 7;
 	gf = 13;
+#else
+	/* 40 bit BCH, for i.MX6UL */
+	m  = 32;
+	b0 = 128;
+	e0 = 40;
+	bn = 128;
+	en = 40;
+	n  = 7;
+	gf = 13;
+#endif
 
 	/* sanity check */
 	/* nand data block must be large enough for FCB structure */
@@ -365,7 +388,7 @@ static void create_dbbt(struct mtd_info *nand, uint8_t *buf)
 static int do_write_bcb(cmd_tbl_t *cmdtp, int flag, int argc,
 			char * const argv[])
 {
-	int j, k, ret;
+	int j, ret;
 	uint8_t *buf;
 	size_t rwsize, maxsize;
 	ulong fw1_off, fw2_off;
@@ -398,7 +421,10 @@ static int do_write_bcb(cmd_tbl_t *cmdtp, int flag, int argc,
 	rwsize = maxsize = nand->writesize;
 
 	off = 0;
-	for(j = 0; j < BOOT_SEARCH_COUNT; j++) {
+	for (j = 0; j < BOOT_SEARCH_COUNT; j++) {
+#ifdef USE_RANDOMIZER
+		int k;
+		/* do randomizer */
 		for (k = 0; k < nand->writesize + nand->oobsize; k++) {
 			*(uint8_t *)(buf + k) ^=
 			RandData[k + ((j * PAGES_PER_STRIDE) % 256)
@@ -409,13 +435,16 @@ static int do_write_bcb(cmd_tbl_t *cmdtp, int flag, int argc,
 #ifdef DEBUG
 		printf("Randomized\n"); dump(buf, 512);
 #endif
+#endif /* USE_RANDOMIZER */
 		ret = raw_access(nand, (ulong) buf, off, 1, 0);
+#ifdef USE_RANDOMIZER
 		/* revert randomizer */
 		for (k = 0; k < nand->writesize + nand->oobsize; k++) {
 			*(uint8_t *)(buf + k) ^=
 			RandData[k + ((j * PAGES_PER_STRIDE) % 256)
 			/ 64 * RAND_16K];
 		}
+#endif /* USE_RANDOMIZER */
 
 		printf("FCB %d bytes written to 0x%x: %s\n", rwsize,
 				(unsigned) off, ret ? "ERROR" : "OK");