diff options
| author | Peng Fan <Peng.Fan@freescale.com> | 2015-06-11 18:19:45 +0800 |
|---|---|---|
| committer | Max Krummenacher <max.krummenacher@toradex.com> | 2016-03-09 14:42:39 +0100 |
| commit | 34fb04a037d5dbfe52d50b2af72e5921d9ab1af5 (patch) | |
| tree | 44feda772107634550e9008f07276e60a74f34ca /arch | |
| parent | cdcdeb00253a12069dfe412ab313554605d303e9 (diff) | |
MLK-11028 imx: mx6qp change L2 prefetch offset to 0
Change L2 prefetch offset to 0 to make system stable.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/cpu/armv7/mx6/soc.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index febf96e03a..0375996af5 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -985,7 +985,7 @@ void v7_outer_cache_enable(void) /* Turn on the L2 I/D prefetch, double linefill */ /* Set prefetch offset with any value except 23 as per errata 765569 */ - val |= 0x7000000f; + val |= 0x70000000; /* * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0 |