diff options
| author | Peng Fan <peng.fan@nxp.com> | 2018-11-15 13:17:37 +0800 |
|---|---|---|
| committer | Peng Fan <peng.fan@nxp.com> | 2018-11-15 16:36:44 +0800 |
| commit | c96a9844cd3342f6e31627ccc4f3e63544ffd78e (patch) | |
| tree | 48dece197699892008a3049640f97df5ad52d837 /arch | |
| parent | e1610fa574b20794c184e00d86c9d0f7505672f1 (diff) | |
MLK-20373-4 imx8: update mem map table
Update mem map table for xen uboot.
xen console and some magic pages needs to be mappe as normal memory.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Flynn xu <flynn.xu@nxp.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-imx/imx8/cpu.c | 29 |
1 files changed, 20 insertions, 9 deletions
diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c index 6f4692e43a..d7eb03086b 100644 --- a/arch/arm/mach-imx/imx8/cpu.c +++ b/arch/arm/mach-imx/imx8/cpu.c @@ -1549,20 +1549,31 @@ void enable_caches(void) if (IS_ENABLED(CONFIG_XEN)) { imx8_mem_map[0].virt = 0x00000000UL; imx8_mem_map[0].phys = 0x00000000UL; - imx8_mem_map[0].size = 0x80000000UL; + imx8_mem_map[0].size = 0x39000000UL; imx8_mem_map[0].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN; - imx8_mem_map[1].virt = 0x80000000UL; - imx8_mem_map[1].phys = 0x80000000UL; - imx8_mem_map[1].size = 0x80000000UL; - imx8_mem_map[1].attrs = (PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE); - - imx8_mem_map[2].virt = 0x100000000UL; - imx8_mem_map[2].phys = 0x100000000UL; - imx8_mem_map[2].size = 0x100000000UL; + imx8_mem_map[1].virt = 0x39000000UL; + imx8_mem_map[1].phys = 0x39000000UL; + imx8_mem_map[1].size = 0x01000000UL; + imx8_mem_map[1].attrs = (PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE); + + imx8_mem_map[2].virt = 0x40000000UL; + imx8_mem_map[2].phys = 0x40000000UL; + imx8_mem_map[2].size = 0x40000000UL; imx8_mem_map[2].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN; + imx8_mem_map[3].virt = 0x80000000UL; + imx8_mem_map[3].phys = 0x80000000UL; + imx8_mem_map[3].size = 0x80000000UL; + imx8_mem_map[3].attrs = (PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE); + + imx8_mem_map[4].virt = 0x100000000UL; + imx8_mem_map[4].phys = 0x100000000UL; + imx8_mem_map[4].size = 0x100000000UL; + imx8_mem_map[4].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN; + icache_enable(); dcache_enable(); |