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authorwdenk <wdenk>2003-06-27 21:31:46 +0000
committerwdenk <wdenk>2003-06-27 21:31:46 +0000
commit8bde7f776c77b343aca29b8c7b58464d915ac245 (patch)
tree20f1fd99975215e7c658454a15cdb4ed4694e2d4 /board/mpl/pip405/init.S
parent993cad9364c6b87ae429d1ed1130d8153f6f027e (diff)
* Code cleanup:LABEL_2003_06_27_2340
- remove trailing white space, trailing empty lines, C++ comments, etc. - split cmd_boot.c (separate cmd_bdinfo.c and cmd_load.c) * Patches by Kenneth Johansson, 25 Jun 2003: - major rework of command structure (work done mostly by Michal Cendrowski and Joakim Kristiansen)
Diffstat (limited to 'board/mpl/pip405/init.S')
-rw-r--r--board/mpl/pip405/init.S7
1 files changed, 3 insertions, 4 deletions
diff --git a/board/mpl/pip405/init.S b/board/mpl/pip405/init.S
index 4a70ec90d8..a0c76dd20b 100644
--- a/board/mpl/pip405/init.S
+++ b/board/mpl/pip405/init.S
@@ -49,7 +49,7 @@
#include <asm/mmu.h>
- .globl ext_bus_cntlr_init
+ .globl ext_bus_cntlr_init
ext_bus_cntlr_init:
mflr r4 /* save link register */
bl ..getAddr
@@ -58,7 +58,7 @@ ext_bus_cntlr_init:
mtlr r4 /* restore link register */
addi r4,0,14 /* set ctr to 14; used to prefetch */
mtctr r4 /* 14 cache lines to fit this function */
- /* in cache (gives us 8x14=112 instrctns) */
+ /* in cache (gives us 8x14=112 instrctns) */
..ebcloop:
icbt r0,r3 /* prefetch cache line for addr in r3 */
addi r3,r3,32 /* move to next cache line */
@@ -211,10 +211,9 @@ ext_bus_cntlr_init:
* Description: Configures the internal SRAM memory. and setup the
* Stackpointer in it.
*----------------------------------------------------------------------------- */
- .globl sdram_init
+ .globl sdram_init
sdram_init:
blr
-