summaryrefslogtreecommitdiff
path: root/board/toradex/apalis-tk1/apalis-tk1.c
diff options
context:
space:
mode:
authorMarcel Ziswiler <marcel.ziswiler@toradex.com>2017-08-04 16:02:30 +0200
committerStefan Agner <stefan.agner@toradex.com>2017-08-31 19:57:22 -0700
commit60b8a4fb2e3a5ccb1d610e1c7bed6da8e08ebba3 (patch)
tree3725dc5f4ff9f6ab78e929fa6e7ea236a89cf5f8 /board/toradex/apalis-tk1/apalis-tk1.c
parent1c66942023d4d056a43fd1c65592ff3ef28156e4 (diff)
pci: tegra: introduce weak tegra_pcie_board_port_reset() function
Introduce a weak tegra_pcie_board_port_reset() function by default calling the existing tegra_pcie_port_reset() function. Additionally add a tegra_pcie_port_index_of_port() function to retrieve the specific PCIe port index if required. This allows overriding the PCIe port reset functionality from board specific code as e.g. required for Apalis T30 and Apalis TK1. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Acked-by: Stephen Warren <swarren@nvidia.com> Acked-by: Stefan Agner <stefan.agner@toradex.com>
Diffstat (limited to 'board/toradex/apalis-tk1/apalis-tk1.c')
-rw-r--r--board/toradex/apalis-tk1/apalis-tk1.c180
1 files changed, 108 insertions, 72 deletions
diff --git a/board/toradex/apalis-tk1/apalis-tk1.c b/board/toradex/apalis-tk1/apalis-tk1.c
index 4ce9d6909b..7f554e455f 100644
--- a/board/toradex/apalis-tk1/apalis-tk1.c
+++ b/board/toradex/apalis-tk1/apalis-tk1.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016 Toradex, Inc.
+ * Copyright (c) 2016-2017 Toradex, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -10,12 +10,20 @@
#include <asm/io.h>
#include <asm/arch/gpio.h>
#include <asm/arch/pinmux.h>
+#include <pci_tegra.h>
#include <power/as3722.h>
#include "../common/tdx-common.h"
#include "pinmux-config-apalis-tk1.h"
-#define LAN_RESET_N TEGRA_GPIO(S, 2)
+#define LAN_DEV_OFF_N TEGRA_GPIO(O, 6)
+#define LAN_RESET_N TEGRA_GPIO(S, 2)
+#define LAN_WAKE_N TEGRA_GPIO(O, 5)
+#ifdef CONFIG_APALIS_TK1_PCIE_EVALBOARD_INIT
+#define PEX_PERST_N TEGRA_GPIO(DD, 1) /* Apalis GPIO7 */
+#define RESET_MOCI_CTRL TEGRA_GPIO(U, 4)
+#endif /* CONFIG_APALIS_TK1_PCIE_EVALBOARD_INIT */
+
#define IXORA_FAN_GPIO TEGRA_GPIO(DD, 2)
int arch_misc_init(void)
@@ -98,83 +106,111 @@ int tegra_pcie_board_init(void)
return err;
}
- /* Reset I210 Gigabit Ethernet Controller */
+ gpio_request(LAN_DEV_OFF_N, "LAN_DEV_OFF_N");
gpio_request(LAN_RESET_N, "LAN_RESET_N");
- gpio_direction_output(LAN_RESET_N, 0);
-
- /*
- * Make sure we don't get any back feeding from LAN_WAKE_N resp.
- * DEV_OFF_N
- */
- gpio_request(TEGRA_GPIO(O, 5), "LAN_WAKE_N");
- gpio_direction_output(TEGRA_GPIO(O, 5), 0);
-
- gpio_request(TEGRA_GPIO(O, 6), "LAN_DEV_OFF_N");
- gpio_direction_output(TEGRA_GPIO(O, 6), 0);
-
- /* Make sure LDO9 and LDO10 are initially enabled @ 0V */
- err = as3722_ldo_enable(pmic, 9);
- if (err < 0) {
- error("failed to enable LDO9: %d\n", err);
- return err;
- }
- err = as3722_ldo_enable(pmic, 10);
- if (err < 0) {
- error("failed to enable LDO10: %d\n", err);
- return err;
- }
- err = as3722_ldo_set_voltage(pmic, 9, 0x80);
- if (err < 0) {
- error("failed to set LDO9 voltage: %d\n", err);
- return err;
- }
- err = as3722_ldo_set_voltage(pmic, 10, 0x80);
- if (err < 0) {
- error("failed to set LDO10 voltage: %d\n", err);
- return err;
- }
+ gpio_request(LAN_WAKE_N, "LAN_WAKE_N");
- mdelay(100);
-
- /* Make sure controller gets enabled by disabling DEV_OFF_N */
- gpio_set_value(TEGRA_GPIO(O, 6), 1);
-
- /* Enable LDO9 and LDO10 for +V3.3_ETH on patched prototypes */
- err = as3722_ldo_set_voltage(pmic, 9, 0xff);
- if (err < 0) {
- error("failed to set LDO9 voltage: %d\n", err);
- return err;
- }
- err = as3722_ldo_set_voltage(pmic, 10, 0xff);
- if (err < 0) {
- error("failed to set LDO10 voltage: %d\n", err);
- return err;
- }
-
- mdelay(100);
- gpio_set_value(LAN_RESET_N, 1);
-
-#ifdef APALIS_TK1_PCIE_EVALBOARD_INIT
-#define PEX_PERST_N TEGRA_GPIO(DD, 1) /* Apalis GPIO7 */
-#define RESET_MOCI_CTRL TEGRA_GPIO(U, 4)
-
- /* Reset PLX PEX 8605 PCIe Switch plus PCIe devices on Apalis Evaluation
- Board */
+#ifdef CONFIG_APALIS_TK1_PCIE_EVALBOARD_INIT
gpio_request(PEX_PERST_N, "PEX_PERST_N");
gpio_request(RESET_MOCI_CTRL, "RESET_MOCI_CTRL");
- gpio_direction_output(PEX_PERST_N, 0);
- gpio_direction_output(RESET_MOCI_CTRL, 0);
- /* Must be asserted for 100 ms after power and clocks are stable */
- mdelay(100);
- gpio_set_value(PEX_PERST_N, 1);
- /* Err_5: PEX_REFCLK_OUTpx/nx Clock Outputs is not Guaranteed Until
- 900 us After PEX_PERST# De-assertion */
- mdelay(1);
- gpio_set_value(RESET_MOCI_CTRL, 1);
-#endif /* APALIS_T30_PCIE_EVALBOARD_INIT */
+#endif /* CONFIG_APALIS_TK1_PCIE_EVALBOARD_INIT */
return 0;
}
+
+void tegra_pcie_board_port_reset(struct tegra_pcie_port *port)
+{
+ int index = tegra_pcie_port_index_of_port(port);
+ if (index == 1) { /* I210 Gigabit Ethernet Controller (On-module) */
+ struct udevice *pmic;
+ int err;
+
+ err = as3722_init(&pmic);
+ if (err) {
+ error("failed to initialize AS3722 PMIC: %d\n", err);
+ return;
+ }
+
+ /* Reset I210 Gigabit Ethernet Controller */
+ gpio_direction_output(LAN_RESET_N, 0);
+
+ /*
+ * Make sure we don't get any back feeding from DEV_OFF_N resp.
+ * LAN_WAKE_N
+ */
+ gpio_direction_output(LAN_DEV_OFF_N, 0);
+ gpio_direction_output(LAN_WAKE_N, 0);
+
+ /* Make sure LDO9 and LDO10 are initially enabled @ 0V */
+ err = as3722_ldo_enable(pmic, 9);
+ if (err < 0) {
+ error("failed to enable LDO9: %d\n", err);
+ return;
+ }
+ err = as3722_ldo_enable(pmic, 10);
+ if (err < 0) {
+ error("failed to enable LDO10: %d\n", err);
+ return;
+ }
+ err = as3722_ldo_set_voltage(pmic, 9, 0x80);
+ if (err < 0) {
+ error("failed to set LDO9 voltage: %d\n", err);
+ return;
+ }
+ err = as3722_ldo_set_voltage(pmic, 10, 0x80);
+ if (err < 0) {
+ error("failed to set LDO10 voltage: %d\n", err);
+ return;
+ }
+
+ /* Make sure controller gets enabled by disabling DEV_OFF_N */
+ gpio_set_value(LAN_DEV_OFF_N, 1);
+
+ /*
+ * Enable LDO9 and LDO10 for +V3.3_ETH on patched prototype
+ * V1.0A and sample V1.0B and newer modules
+ */
+ err = as3722_ldo_set_voltage(pmic, 9, 0xff);
+ if (err < 0) {
+ error("failed to set LDO9 voltage: %d\n", err);
+ return;
+ }
+ err = as3722_ldo_set_voltage(pmic, 10, 0xff);
+ if (err < 0) {
+ error("failed to set LDO10 voltage: %d\n", err);
+ return;
+ }
+
+ /*
+ * Must be asserted for 100 ms after power and clocks are stable
+ */
+ mdelay(100);
+
+ gpio_set_value(LAN_RESET_N, 1);
+ } else if (index == 0) { /* Apalis PCIe */
+#ifdef CONFIG_APALIS_TK1_PCIE_EVALBOARD_INIT
+ /*
+ * Reset PLX PEX 8605 PCIe Switch plus PCIe devices on Apalis
+ * Evaluation Board
+ */
+ gpio_direction_output(PEX_PERST_N, 0);
+ gpio_direction_output(RESET_MOCI_CTRL, 0);
+
+ /*
+ * Must be asserted for 100 ms after power and clocks are stable
+ */
+ mdelay(100);
+
+ gpio_set_value(PEX_PERST_N, 1);
+ /*
+ * Err_5: PEX_REFCLK_OUTpx/nx Clock Outputs is not Guaranteed
+ * Until 900 us After PEX_PERST# De-assertion
+ */
+ mdelay(1);
+ gpio_set_value(RESET_MOCI_CTRL, 1);
+#endif /* CONFIG_APALIS_TK1_PCIE_EVALBOARD_INIT */
+ }
+}
#endif /* CONFIG_PCI_TEGRA */
void start_cpu_fan(void)