diff options
| author | Stefan Agner <stefan.agner@toradex.com> | 2014-03-11 17:41:00 +0100 |
|---|---|---|
| committer | Stefan Agner <stefan@agner.ch> | 2014-04-23 18:10:40 +0200 |
| commit | 3f0c6cd0ce089f77c376b8b1d4b9edc7d8a10e41 (patch) | |
| tree | d97e455aa9639eddc18617bf726d57a8624ae153 /board | |
| parent | dda0dbfc69f3d560c87f5be85f127ed862ea6721 (diff) | |
arm: vf610: add DDR_SEL_PAD_CONTR register
Set DDR_SEL_PAD_CONTR register explicitly to DDR3 which solves DDR3
issues with newer silicon (1.1). This register was added in revision
4 of the Vybrid Reference Manual.
Diffstat (limited to 'board')
| -rw-r--r-- | board/freescale/vf610twr/vf610twr.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/board/freescale/vf610twr/vf610twr.c b/board/freescale/vf610twr/vf610twr.c index 4ee74c0198..d64d3aa872 100644 --- a/board/freescale/vf610twr/vf610twr.c +++ b/board/freescale/vf610twr/vf610twr.c @@ -217,7 +217,8 @@ void ddr_ctrl_init(void) &ddrmr->cr[139]); writel(DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(13) | - DDRMC_CR154_PAD_ZQ_MODE(1), &ddrmr->cr[154]); + DDRMC_CR154_PAD_ZQ_MODE(1) | + DDRMC_CR154_DDR_SEL_PAD_CONTR(3), &ddrmr->cr[154]); writel(DDRMC_CR155_AXI0_AWCACHE | DDRMC_CR155_PAD_ODT_BYTE1(2), &ddrmr->cr[155]); writel(DDRMC_CR158_TWR(6), &ddrmr->cr[158]); |