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authorVignesh R <vigneshr@ti.com>2016-11-05 16:05:16 +0530
committerTom Rini <trini@konsulko.com>2016-11-13 15:54:37 -0500
commit948b8bbd5fc4722ec10e0ffde29d31d982f6a6e4 (patch)
treebb63e2efb3fd580df536632e9daa609862c91afe /drivers
parent84295f2a202b6c062ec17e148e3418af0db795f5 (diff)
spi: ti_qspi: Fix baudrate divider calculation
Fix the divider calculation logic to choose a value so that the resulting baudrate is either equal to or closest possible baudrate less than the requested value. While at that, cleanup ti_spi_set_speed(). Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/spi/ti_qspi.c16
1 files changed, 7 insertions, 9 deletions
diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
index 52520dff63..da04886590 100644
--- a/drivers/spi/ti_qspi.c
+++ b/drivers/spi/ti_qspi.c
@@ -16,6 +16,7 @@
#include <asm/omap_gpio.h>
#include <asm/omap_common.h>
#include <asm/ti-common/ti-edma3.h>
+#include <linux/kernel.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -118,21 +119,18 @@ static void ti_spi_set_speed(struct ti_qspi_priv *priv, uint hz)
if (!hz)
clk_div = 0;
else
- clk_div = (priv->fclk / hz) - 1;
+ clk_div = DIV_ROUND_UP(priv->fclk, hz) - 1;
+
+ /* truncate clk_div value to QSPI_CLK_DIV_MAX */
+ if (clk_div > QSPI_CLK_DIV_MAX)
+ clk_div = QSPI_CLK_DIV_MAX;
debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div);
/* disable SCLK */
writel(readl(&priv->base->clk_ctrl) & ~QSPI_CLK_EN,
&priv->base->clk_ctrl);
-
- /* assign clk_div values */
- if (clk_div < 0)
- clk_div = 0;
- else if (clk_div > QSPI_CLK_DIV_MAX)
- clk_div = QSPI_CLK_DIV_MAX;
-
- /* enable SCLK */
+ /* enable SCLK and program the clk divider */
writel(QSPI_CLK_EN | clk_div, &priv->base->clk_ctrl);
}