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authorMarcel Ziswiler <marcel.ziswiler@toradex.com>2015-08-18 10:51:00 +0200
committerMarcel Ziswiler <marcel.ziswiler@toradex.com>2015-08-18 10:51:00 +0200
commitf7c3186985ebb244d075b04ed7c055f39f485670 (patch)
tree92f9b896ae3e5073e4cf9f47c82626e3d27f77b7 /include
parentf9e7649338178f823e291386dde5086ad636b703 (diff)
colibri_t20: implement early pmic rail configuration
Implement early TPS6586X PMIC rail configuration setting SM0 being VDD_CORE_1.2V to 1.2 volts and SM1 being VDD_CPU_1.0V to 1.0 volts. While those are PMIC power-up defaults the SoC might have been reset separately with certain rails being left at lower DVFS states which is e.g. the case upon watchdog reset while otherwise nearly idling.
Diffstat (limited to 'include')
-rw-r--r--include/configs/colibri_t20.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/include/configs/colibri_t20.h b/include/configs/colibri_t20.h
index 0aa07959c8..63e832dd6c 100644
--- a/include/configs/colibri_t20.h
+++ b/include/configs/colibri_t20.h
@@ -14,6 +14,8 @@
#undef CONFIG_SYS_DCACHE_OFF /* breaks L4T kernel boot */
#define CONFIG_ARCH_MISC_INIT
+#define CONFIG_TEGRA_EARLY_TPS6586X
+
/* High-level configuration options */
#define V_PROMPT "Colibri T20 # "
#define CONFIG_CUSTOM_BOARDINFO /* not from device-tree model node */