diff options
32 files changed, 458 insertions, 92 deletions
@@ -1,3 +1,348 @@ +commit f7b16a0a4d571dd33b2b5185a54f7ddc311f89d4 +Author: Wolfgang Denk <wd@denx.de> +Date: Tue Apr 29 23:32:20 2008 +0200 + + common/env_nand.c: fix one more incompatible pointer type issue + + Signed-off-by: Wolfgang Denk <wd@denx.de> + +commit ea6f66894f952229eebfc4ad03cd21fe5c8b3f0f +Author: Wolfgang Denk <wd@denx.de> +Date: Tue Apr 29 21:33:08 2008 +0200 + + post/board/lwmon5/sysmon.c: fix manual merge error. + + Signed-off-by: Wolfgang Denk <wd@denx.de> + +commit 70a0f81412b0b18a6fd0bea960451bc6c2cca49a +Author: Kumar Gala <galak@kernel.crashing.org> +Date: Tue Apr 29 12:54:59 2008 -0500 + + 85xx: Add -mno-spe to e500/85xx builds + + Newer gcc's might be configured to enable autovectorization by default. + If we happen to build with one of those compilers we will get SPE + instructions in random code. + + -mno-spe disables the compiler for automatically generating SPE + instructions without our knowledge. + + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + +commit 8ea08e5be69436abcc95d3da114de4a2ff8a6ab5 +Author: Kumar Gala <galak@kernel.crashing.org> +Date: Tue Apr 29 10:18:34 2008 -0500 + + Update .gitignore for zlib.h + + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + +commit 45239cf4152109caa925145ccd433529902df887 +Author: Kumar Gala <galak@kernel.crashing.org> +Date: Tue Apr 29 10:27:08 2008 -0500 + + 85xx/86xx: Rename ext_refrec to timing_cfg_3 to match docs + + All the 85xx and 86xx UM describe the register as timing_cfg_3 + not as ext_refrec. + + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + +commit ef7d30b14394e4c4a153118f5845760cadada02a +Author: Kumar Gala <galak@kernel.crashing.org> +Date: Tue Apr 29 10:28:34 2008 -0500 + + 85xx/86xx: Rename DDR init address and init extended address register + + Rename init_addr and init_ext_addr to match the docs between + 85xx and 86xx. Both now use 'init_addr' and 'init_ext_addr'. + + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + +commit cf6cc014270549684873a5972d2595052c468cb6 +Author: Kumar Gala <galak@kernel.crashing.org> +Date: Mon Apr 28 02:24:04 2008 -0500 + + 85xx: Additional fixes and cleanup of MP code + + * adjust __spin_table alignment to match ePAPR v0.94 spec + * loop over all cpus when determing who is up. This fixes an issue if + the "boot cpu" isn't core0. The "boot cpu" will already be in the + cpu_up_mask so there is no harm + * Added some protection in the code to ensure proper behavior. These + changes are explicitly needed but don't hurt: + - Added eieio to ensure the "hot word" of the table is written after + all other table updates have occurred. + - Added isync to ensure we don't prefetch loading of table entries + until we a released + + These issues we raised by Dave Liu. + + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + +commit b2d527a8b9fb50afccbaf79b5540952585cdc760 +Author: Yuri Tikhonov <yur@emcraft.com> +Date: Tue Apr 29 15:06:41 2008 +0200 + + lwmon5: minor clean-up to include/configs/lwmon5.h + + LWMON5 DSPIC POST uses the watch-dog scratch register. So, make + the CFG_DSPIC_TEST_ADDR definition more readable. + + Signed-off-by: Yuri Tikhonov <yur@emcraft.com> + +commit f4c4d21a885ccc222fd0acdf653b683249e85117 +Author: Stefan Roese <sr@denx.de> +Date: Tue Apr 29 16:08:05 2008 +0200 + + ppc4xx: Fix CFG_MONITOR_LEN on Katmai failsave this time + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit 138105efe1d2b1a40a3a97b4c1f85c2111bea2d8 +Author: Yuri Tikhonov <yur@emcraft.com> +Date: Tue Apr 29 13:32:45 2008 +0200 + + ppc flush_cache: add watch-dog triggering into the loops. + + Some boards (e.g. lwmon5) need rather a frequent watch-dog + kicking. Since the time it takes for the flush_cache() function + to complete its job depends on the size of data being flushed, one + may encounter watch-dog resets on such boards when, for example, + download big files over ethernet. + + Signed-off-by: Yuri Tikhonov <yur@emcraft.com> + +commit cab99d6f3281ab6784feccf98b9b425daa58418a +Author: Stefan Roese <sr@denx.de> +Date: Tue Apr 29 14:44:54 2008 +0200 + + ppc4xx: Fix compilation warning in denali_spd_ddr2.c + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit 4ec9d78fe5cd585d2868731fa108ca1e62730e70 +Author: Stefan Roese <sr@denx.de> +Date: Tue Apr 29 14:12:07 2008 +0200 + + ppc4xx: Fix Katmai CFG_MONITOR_LEN + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit 85ad184b3b2b0f8af9228477303c55dca1b52ed7 +Author: Stefan Roese <sr@denx.de> +Date: Tue Apr 29 13:57:07 2008 +0200 + + ppc4xx: Complete remove bogus dflush() + + Since the current dflush() implementation is know to have some problems + (as seem on lwmon5 ECC init) this patch removes it completely and replaces + it by using clean_dcache_range(). + + Tested on Katmai with ECC DIMM. + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit 135846d6ecaad255ad28d93ebbb78b3d5da68cdc +Author: Stefan Roese <sr@denx.de> +Date: Tue Apr 29 13:36:51 2008 +0200 + + ppc4xx: Change ECC initialization on lwmon5 to use clean_dcache_range() + + As it seems the "old" ECC initialization routine by using dflush() didn't + write all lines in the dcache back to memory on lwmon5. This could lead + to ECC error upon Linux booting. This patch changes the program_ecc() + routine to now use clean_dcache_range() instead of dflush(). + clean_dcache_range() uses dcbst which is exactly what we want in this + case. + + Since dflush() is known is cause problems, this routine will be + removed completely and replaced by clean_dcache_range() with an + additional patch. + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit 18ec19e4aa1a045dfbf2c7c2e33963488e92d757 +Author: Yuri Tikhonov <yur@emcraft.com> +Date: Mon Apr 28 18:19:34 2008 +0200 + + POST: fix Makefiles for mpc8xx, lwmon, and netta POSTs. + + Signed-off-by: Yuri Tikhonov <yur@emcraft.com> + +commit eea5a743a2193ef2a05b9bc6dc447ba241416f35 +Author: Markus Brunner <super.firetwister@googlemail.com> +Date: Mon Apr 28 08:47:47 2008 +0200 + + ppc4xx: Fixup ebc clock in FDT for 405GP/EP + + On ppc405EP and ppc405GP (at least) the ebc is directly attached to the plb + and not to the opb. This patch will try to fixup /plb/ebc if /plb/opb/ebc + doesn't exist. + + Signed-off-by: Markus Brunner <super.firetwister@gmail.com> + +commit 707fa917cca24c0f22776f48ac4a6fa5e5189b10 +Author: Wolfgang Denk <wd@denx.de> +Date: Mon Apr 28 22:01:04 2008 +0200 + + jffs2_1pass.c: fix incompatible pointer type warning + + Signed-off-by: Wolfgang Denk <wd@denx.de> + +commit 6aee00f5e6a1cf29d8fe8fdc9b7252fbd31115d9 +Author: Sascha Laue <Sascha.Laue@gmx.biz> +Date: Tue Apr 1 10:10:18 2008 +0200 + + lwmon5: update dsPIC POST spezification + + The specification for the lwmon5 board dsPIC POST got changed. + Also add defines for the temperatures and voltages. + + Signed-off-by: Sascha Laue <sascha.laue@liebherr.com> + +commit 3e4615ab7ff38781a5dd80d0f49b9af55b4fe0b7 +Author: Sascha Laue <Sascha.Laue@gmx.biz> +Date: Tue Apr 1 15:13:03 2008 +0200 + + Fix watchdog POST for lwmon5 + + If the hardware watchdog detects a voltage error, the watchdog sets + GPIO62 to low. The watchdog POST has to detect this low level. + + Signed-off-by: Sascha Laue <leglas0@legpc180.leg.liebherr.i> + Signed-off-by: Wolfgang Denk <wd@denx.de> + +commit dd5748bcd669f46aeb6686c1b341323843738ccc +Author: Guennadi Liakhovetski <g.liakhovetski@gmx.de> +Date: Mon Apr 28 14:37:14 2008 +0200 + + rtl8169: fix compiler warnings + + Fix multiple compiler warnings related to argument type mismatch. + + Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> + +commit 413bf586266f86c6bdbc6c6d140f67a15af4c4f1 +Author: Guennadi Liakhovetski <g.liakhovetski@gmx.de> +Date: Mon Apr 28 14:36:06 2008 +0200 + + IDE: fix compiler warnings + + The IDE driver can use 32-bit addresses in LBA mode, in which case it + spits multiple warnings during compilation. Fix them. + + Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> + +commit db9084de28c46ac81c8f681722cb0d7411be4d7f +Author: Guennadi Liakhovetski <g.liakhovetski@gmx.de> +Date: Mon Apr 28 14:35:57 2008 +0200 + + LinkStation: fix compiler warning, add a maintainer + + out_8 wants a pointer to an unsigned as the first argument. Add a + maintainer for Linkstation boards. + + Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> + +commit c71abba3cb67b063f789f17abf6c7447727c0cd5 +Author: Wolfgang Denk <wd@denx.de> +Date: Mon Apr 28 14:55:12 2008 +0200 + + cmd_nand.c: fix "differ in signedness" problem + + Signed-off-by: Wolfgang Denk <wd@denx.de> + +commit f2c288a35341ad02ac03b1563d786763c9c8f159 +Author: Wolfgang Denk <wd@denx.de> +Date: Mon Apr 28 12:48:47 2008 +0200 + + pcnet.c: fix a merge issue + + Signed-off-by: Wolfgang Denk <wd@denx.de> + +commit 4ca79f477ebd25a6872e6196d80e2f5eff441376 +Author: Wolfgang Denk <wd@denx.de> +Date: Mon Apr 28 12:08:18 2008 +0200 + + NAND: fix some strict-aliasing compiler warnings + + Signed-off-by: Wolfgang Denk <wd@denx.de> + +commit 5cd0130ecc79d6dcde1b1ac253abc457ca8c3115 +Author: Stefan Roese <sr@denx.de> +Date: Mon Apr 28 11:37:14 2008 +0200 + + ppc4xx: Fix compile warning of hcu4 board + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit 5379cd15dd6c74ac51499bce3455bf6e0cdbe9f1 +Author: Wolfgang Denk <wd@denx.de> +Date: Mon Apr 28 11:31:23 2008 +0200 + + MPC8323ERDB: fix implicit declaration of function 'mac_read_from_eeprom' + + Signed-off-by: Wolfgang Denk <wd@denx.de> + +commit 7602ed50a2f0ef3dc8d7da93f116de50288f5b59 +Author: Guennadi Liakhovetski <lg@denx.de> +Date: Mon Apr 28 00:25:32 2008 +0200 + + mx31ads: fix loadaddr environment variable define + + Arithmetic expressions do not get evaluated under stringification. Remove + default network configuration, add DHCP command support. Thanks to Felix + Radensky for reporting. + + Signed-off-by: Guennadi Liakhovetski <lg@denx.de> + +commit 144eec777ac07bcb12bd38245a5a289f694a7f98 +Author: Wolfgang Denk <wd@denx.de> +Date: Mon Apr 28 10:55:24 2008 +0200 + + katmai: fix section overlap problem + + Since we didn't want to remove features from the configuration, we + decided to increase the U-Boot image size (add one flash sector). + + Also changed the default environment definition to make it + independent of such changes. + + Signed-off-by: Wolfgang Denk <wd@denx.de> + Acked-by: Stefan Roese <sr@denx.de> + +commit 941d696d25624e3cc65ebf924199541acf52d74e +Author: Wolfgang Denk <wd@denx.de> +Date: Mon Apr 28 10:55:24 2008 +0200 + + katmai: fix section overlap problem + + Since we didn't want to remove features from the configuration, we + decided to increase the U-Boot image size (add one flash sector). + + Also changed the default environment definition to make it + independent of such changes. + + Signed-off-by: Wolfgang Denk <wd@denx.de> + Acked-by: Stefan Roese <sr@denx.de> + +commit 03c6cd39f9184143fd8c537872b3d4b2e03f1466 +Author: Kumar Gala <galak@kernel.crashing.org> +Date: Sat Apr 26 11:44:44 2008 -0500 + + post: Fix building with O= + + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + +commit fd7531c1e9d56b9e5e06d2c0e02b798dab72f70c +Author: Wolfgang Denk <wd@denx.de> +Date: Sat Apr 26 01:55:00 2008 +0200 + + Prepare v1.3.3-rc1 + + Signed-off-by: Wolfgang Denk <wd@denx.de> + commit 19cf2ec90d8ce52da60c1693693c4048cb810967 Author: Wolfgang Denk <wd@denx.de> Date: Sat Apr 26 01:25:39 2008 +0200 @@ -24,7 +24,7 @@ VERSION = 1 PATCHLEVEL = 3 SUBLEVEL = 3 -EXTRAVERSION = -rc1 +EXTRAVERSION = -rc2 U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION) VERSION_FILE = $(obj)include/version_autogenerated.h diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd.c b/board/freescale/mpc8610hpcd/mpc8610hpcd.c index d9a740ee0d..3a855b5903 100644 --- a/board/freescale/mpc8610hpcd/mpc8610hpcd.c +++ b/board/freescale/mpc8610hpcd/mpc8610hpcd.c @@ -192,7 +192,7 @@ long int fixed_sdram(void) ddr->cs0_bnds = 0x0000001f; ddr->cs0_config = 0x80010202; - ddr->ext_refrec = 0x00000000; + ddr->timing_cfg_3 = 0x00000000; ddr->timing_cfg_0 = 0x00260802; ddr->timing_cfg_1 = 0x3935d322; ddr->timing_cfg_2 = 0x14904cc8; diff --git a/board/freescale/mpc8641hpcn/mpc8641hpcn.c b/board/freescale/mpc8641hpcn/mpc8641hpcn.c index 31e7d67d04..bb1f927b95 100644 --- a/board/freescale/mpc8641hpcn/mpc8641hpcn.c +++ b/board/freescale/mpc8641hpcn/mpc8641hpcn.c @@ -130,7 +130,7 @@ fixed_sdram(void) ddr->cs0_bnds = CFG_DDR_CS0_BNDS; ddr->cs0_config = CFG_DDR_CS0_CONFIG; - ddr->ext_refrec = CFG_DDR_EXT_REFRESH; + ddr->timing_cfg_3 = CFG_DDR_TIMING_3; ddr->timing_cfg_0 = CFG_DDR_TIMING_0; ddr->timing_cfg_1 = CFG_DDR_TIMING_1; ddr->timing_cfg_2 = CFG_DDR_TIMING_2; diff --git a/board/lwmon5/sdram.c b/board/lwmon5/sdram.c index 7c3cf496be..36b51007ea 100644 --- a/board/lwmon5/sdram.c +++ b/board/lwmon5/sdram.c @@ -34,6 +34,7 @@ #include <asm/processor.h> #include <asm/mmu.h> #include <asm/io.h> +#include <asm/cache.h> #include <ppc440.h> #include <watchdog.h> @@ -59,7 +60,6 @@ extern int denali_wait_for_dlllock(void); extern void denali_core_search_data_eye(void); extern void dcbz_area(u32 start_address, u32 num_bytes); -extern void dflush(void); static u32 is_ecc_enabled(void) { @@ -106,6 +106,7 @@ static void program_ecc(u32 start_address, { u32 val; u32 current_addr = start_address; + u32 size; int bytes_remaining; sync(); @@ -123,12 +124,18 @@ static void program_ecc(u32 start_address, * watchdog. */ while (bytes_remaining > 0) { - dcbz_area(current_addr, min((64 << 20), bytes_remaining)); + size = min((64 << 20), bytes_remaining); + + /* Write zero's to SDRAM */ + dcbz_area(current_addr, size); + + /* Write modified dcache lines back to memory */ + clean_dcache_range(current_addr, current_addr + size); + current_addr += 64 << 20; bytes_remaining -= 64 << 20; WATCHDOG_RESET(); } - dflush(); sync(); wait_ddr_idle(); diff --git a/board/netstal/hcu5/sdram.c b/board/netstal/hcu5/sdram.c index 0b16b50502..6b1b53a4d0 100644 --- a/board/netstal/hcu5/sdram.c +++ b/board/netstal/hcu5/sdram.c @@ -34,11 +34,11 @@ #include <asm/processor.h> #include <asm/io.h> #include <asm/mmu.h> +#include <asm/cache.h> #include <ppc440.h> void hcu_led_set(u32 value); void dcbz_area(u32 start_address, u32 num_bytes); -void dflush(void); #define DDR_DCR_BASE 0x10 #define ddrcfga (DDR_DCR_BASE+0x0) /* DDR configuration address reg */ @@ -185,14 +185,14 @@ static void program_ecc(unsigned long start_address, unsigned long num_bytes) #endif sync(); - eieio(); puts(str); /* ECC bit set method for cached memory */ /* Fast method, no noticeable delay */ dcbz_area(start_address, num_bytes); - dflush(); + /* Write modified dcache lines back to memory */ + clean_dcache_range(start_address, start_address + num_bytes); blank_string(strlen(str)); /* Clear error status */ diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c index 8a6ced3864..46496da60b 100644 --- a/board/sbc8548/sbc8548.c +++ b/board/sbc8548/sbc8548.c @@ -299,7 +299,7 @@ long int fixed_sdram (void) ddr->cs1_config = 0x80010101; ddr->cs2_config = 0x00000000; ddr->cs3_config = 0x00000000; - ddr->ext_refrec = 0x00000000; + ddr->timing_cfg_3 = 0x00000000; ddr->timing_cfg_0 = 0x00220802; ddr->timing_cfg_1 = 0x38377322; ddr->timing_cfg_2 = 0x0fa044C7; diff --git a/board/sbc8641d/sbc8641d.c b/board/sbc8641d/sbc8641d.c index b3dd9c8657..519f332784 100644 --- a/board/sbc8641d/sbc8641d.c +++ b/board/sbc8641d/sbc8641d.c @@ -135,7 +135,7 @@ long int fixed_sdram (void) ddr->cs1_config = CFG_DDR_CS1_CONFIG; ddr->cs2_config = CFG_DDR_CS2_CONFIG; ddr->cs3_config = CFG_DDR_CS3_CONFIG; - ddr->ext_refrec = CFG_DDR_EXT_REFRESH; + ddr->timing_cfg_3 = CFG_DDR_TIMING_3; ddr->timing_cfg_0 = CFG_DDR_TIMING_0; ddr->timing_cfg_1 = CFG_DDR_TIMING_1; ddr->timing_cfg_2 = CFG_DDR_TIMING_2; @@ -166,7 +166,7 @@ long int fixed_sdram (void) ddr->cs1_config = CFG_DDR2_CS1_CONFIG; ddr->cs2_config = CFG_DDR2_CS2_CONFIG; ddr->cs3_config = CFG_DDR2_CS3_CONFIG; - ddr->ext_refrec = CFG_DDR2_EXT_REFRESH; + ddr->timing_cfg_3 = CFG_DDR2_EXT_REFRESH; ddr->timing_cfg_0 = CFG_DDR2_TIMING_0; ddr->timing_cfg_1 = CFG_DDR2_TIMING_1; ddr->timing_cfg_2 = CFG_DDR2_TIMING_2; diff --git a/common/env_nand.c b/common/env_nand.c index b6a5b4aaab..0dddddf0a1 100644 --- a/common/env_nand.c +++ b/common/env_nand.c @@ -211,7 +211,7 @@ int saveenv(void) void env_relocate_spec (void) { #if !defined(ENV_IS_EMBEDDED) - ulong total; + size_t total; int crc1_ok = 0, crc2_ok = 0; env_t *tmp_env1, *tmp_env2; diff --git a/cpu/mpc85xx/config.mk b/cpu/mpc85xx/config.mk index f6df702e52..9e574a20d0 100644 --- a/cpu/mpc85xx/config.mk +++ b/cpu/mpc85xx/config.mk @@ -25,3 +25,4 @@ PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx -DCONFIG_E500 -ffixed-r2 \ -Wa,-me500 -msoft-float -mno-string +PLATFORM_CPPFLAGS +=$(call cc-option,-mno-spe) diff --git a/cpu/mpc85xx/mp.c b/cpu/mpc85xx/mp.c index e733f7b00a..a527cf3047 100644 --- a/cpu/mpc85xx/mp.c +++ b/cpu/mpc85xx/mp.c @@ -103,6 +103,10 @@ int cpu_release(int nr, int argc, char *argv[]) } table[BOOT_ENTRY_ADDR_UPPER] = (u32)(boot_addr >> 32); + + /* ensure all table updates complete before final address write */ + eieio(); + table[BOOT_ENTRY_ADDR_LOWER] = (u32)(boot_addr & 0xffffffff); return 0; @@ -153,7 +157,7 @@ static void pq3_mp_up(unsigned long bootpg) /* wait for everyone */ while (timeout) { int i; - for (i = 1; i < CONFIG_NR_CPUS; i++) { + for (i = 0; i < CONFIG_NR_CPUS; i++) { if (table[i * NUM_BOOT_ENTRY + BOOT_ENTRY_ADDR_LOWER]) cpu_up_mask |= (1 << i); }; diff --git a/cpu/mpc85xx/release.S b/cpu/mpc85xx/release.S index 3b7366ff69..a47edaea62 100644 --- a/cpu/mpc85xx/release.S +++ b/cpu/mpc85xx/release.S @@ -114,6 +114,7 @@ __secondary_start_page: lwz r4,ENTRY_ADDR_LOWER(r10) andi. r11,r4,1 bne 2b + isync /* get the upper bits of the addr */ lwz r11,ENTRY_ADDR_UPPER(r10) @@ -169,7 +170,7 @@ __secondary_start_page: mtspr SPRN_SRR1,r13 rfi - .align 3 + .align L1_CACHE_SHIFT .globl __spin_table __spin_table: .space CONFIG_NR_CPUS*ENTRY_SIZE diff --git a/cpu/mpc85xx/spd_sdram.c b/cpu/mpc85xx/spd_sdram.c index 435458a189..e3a824999c 100644 --- a/cpu/mpc85xx/spd_sdram.c +++ b/cpu/mpc85xx/spd_sdram.c @@ -610,8 +610,8 @@ spd_sdram(void) /* * Sneak in some Extended Refresh Recovery. */ - ddr->ext_refrec = (trfc_high << 16); - debug("DDR: ext_refrec = 0x%08x\n", ddr->ext_refrec); + ddr->timing_cfg_3 = (trfc_high << 16); + debug("DDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3); ddr->timing_cfg_1 = (0 diff --git a/cpu/mpc86xx/spd_sdram.c b/cpu/mpc86xx/spd_sdram.c index 60a7818989..8485841a45 100644 --- a/cpu/mpc86xx/spd_sdram.c +++ b/cpu/mpc86xx/spd_sdram.c @@ -644,8 +644,8 @@ spd_init(unsigned char i2c_address, unsigned int ddr_num, /* * Sneak in some Extended Refresh Recovery. */ - ddr->ext_refrec = (trfc_high << 16); - debug("DDR: ext_refrec = 0x%08x\n", ddr->ext_refrec); + ddr->timing_cfg_3 = (trfc_high << 16); + debug("DDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3); ddr->timing_cfg_1 = (0 diff --git a/cpu/ppc4xx/44x_spd_ddr2.c b/cpu/ppc4xx/44x_spd_ddr2.c index 9e722b9984..5b5de48544 100644 --- a/cpu/ppc4xx/44x_spd_ddr2.c +++ b/cpu/ppc4xx/44x_spd_ddr2.c @@ -40,6 +40,7 @@ #include <asm/io.h> #include <asm/processor.h> #include <asm/mmu.h> +#include <asm/cache.h> #if defined(CONFIG_SPD_EEPROM) && \ (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ @@ -237,7 +238,6 @@ static void DQS_calibration_process(void); static void ppc440sp_sdram_register_dump(void); int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); void dcbz_area(u32 start_address, u32 num_bytes); -void dflush(void); static u32 mfdcr_any(u32 dcr) { @@ -2355,7 +2355,8 @@ static void program_ecc_addr(unsigned long start_address, } else { /* ECC bit set method for cached memory */ dcbz_area(start_address, num_bytes); - dflush(); + /* Write modified dcache lines back to memory */ + clean_dcache_range(start_address, start_address + num_bytes); } blank_string(strlen(str)); diff --git a/cpu/ppc4xx/denali_spd_ddr2.c b/cpu/ppc4xx/denali_spd_ddr2.c index e20c9ebf87..ad805b937b 100644 --- a/cpu/ppc4xx/denali_spd_ddr2.c +++ b/cpu/ppc4xx/denali_spd_ddr2.c @@ -45,6 +45,7 @@ #include <asm/io.h> #include <asm/processor.h> #include <asm/mmu.h> +#include <asm/cache.h> #if defined(CONFIG_SPD_EEPROM) && \ (defined(CONFIG_440EPX) || defined(CONFIG_440GRX)) @@ -92,7 +93,6 @@ extern int denali_wait_for_dlllock(void); extern void denali_core_search_data_eye(void); extern void dcbz_area(u32 start_address, u32 num_bytes); -extern void dflush(void); /* * Board-specific Platform code can reimplement spd_ddr_init_hang () if needed @@ -1201,7 +1201,8 @@ long int initdram(int board_type) #else #error Please define CFG_MEM_TOP_HIDE (see README) in your board config file #endif - dflush(); + /* Write modified dcache lines back to memory */ + clean_dcache_range(CFG_SDRAM_BASE, CFG_SDRAM_BASE + dram_size - CFG_MEM_TOP_HIDE); debug("Completed\n"); sync(); remove_tlb(CFG_SDRAM_BASE, dram_size); diff --git a/cpu/ppc4xx/fdt.c b/cpu/ppc4xx/fdt.c index 1f4d6f27fd..02dece0c0f 100644 --- a/cpu/ppc4xx/fdt.c +++ b/cpu/ppc4xx/fdt.c @@ -83,8 +83,14 @@ void ft_cpu_setup(void *blob, bd_t *bd) bd->bi_intfreq, 1); do_fixup_by_path_u32(blob, "/plb", "clock-frequency", sys_info.freqPLB, 1); do_fixup_by_path_u32(blob, "/plb/opb", "clock-frequency", sys_info.freqOPB, 1); - do_fixup_by_path_u32(blob, "/plb/opb/ebc", "clock-frequency", - sys_info.freqEBC, 1); + + if (fdt_path_offset(blob, "/plb/opb/ebc") >= 0) + do_fixup_by_path_u32(blob, "/plb/opb/ebc", "clock-frequency", + sys_info.freqEBC, 1); + else + do_fixup_by_path_u32(blob, "/plb/ebc", "clock-frequency", + sys_info.freqEBC, 1); + fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); /* diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index 8d2777dcd9..a513b4507a 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -1675,35 +1675,6 @@ trap_reloc: sync blr function_epilog(dcbz_area) - -/*----------------------------------------------------------------------------+ -| dflush. Assume 32K at vector address is cachable. -+----------------------------------------------------------------------------*/ - function_prolog(dflush) - mfmsr r9 - rlwinm r8,r9,0,15,13 - rlwinm r8,r8,0,17,15 - mtmsr r8 - mfspr r8,dvlim - addi r3,r0,0x0000 - mtspr dvlim,r3 - mfspr r3,ivpr - addi r4,r0,1024 - mtctr r4 -..dflush_loop: - lwz r6,0x0(r3) - addi r3,r3,32 - bdnz ..dflush_loop - addi r3,r3,-32 - mtctr r4 -..ag: dcbf r0,r3 - addi r3,r3,-32 - bdnz ..ag - mtspr dvlim,r8 - sync - mtmsr r9 - blr - function_epilog(dflush) #endif /* CONFIG_440 */ #endif /* CONFIG_NAND_SPL */ diff --git a/fs/jffs2/jffs2_1pass.c b/fs/jffs2/jffs2_1pass.c index 69f53eabcf..a3304384f2 100644 --- a/fs/jffs2/jffs2_1pass.c +++ b/fs/jffs2/jffs2_1pass.c @@ -185,11 +185,7 @@ static int read_nand_cached(u32 off, u32 size, u_char *buf) { struct mtdids *id = current_part->dev->id; u32 bytes_read = 0; -#if defined(CFG_NAND_LEGACY) size_t retlen; -#else - ulong retlen; -#endif int cpy_bytes; while (bytes_read < size) { diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h index dc6e278ff4..2d07625464 100644 --- a/include/asm-ppc/immap_85xx.h +++ b/include/asm-ppc/immap_85xx.h @@ -92,7 +92,7 @@ typedef struct ccsr_ddr { uint cs2_config_2; /* 0x20c8 - DDR Chip Select Configuration 2 */ uint cs3_config_2; /* 0x20cc - DDR Chip Select Configuration 2 */ char res5[48]; - uint ext_refrec; /* 0x2100 - DDR SDRAM Extended Refresh Recovery */ + uint timing_cfg_3; /* 0x2100 - DDR SDRAM Timing Configuration Register 3 */ uint timing_cfg_0; /* 0x2104 - DDR SDRAM Timing Configuration Register 0 */ uint timing_cfg_1; /* 0x2108 - DDR SDRAM Timing Configuration Register 1 */ uint timing_cfg_2; /* 0x210c - DDR SDRAM Timing Configuration Register 2 */ @@ -106,8 +106,8 @@ typedef struct ccsr_ddr { char res6[4]; uint sdram_clk_cntl; /* 0x2130 - DDR SDRAM Clock Control */ char res7[20]; - uint init_address; /* 0x2148 - DDR training initialization address */ - uint init_ext_address; /* 0x214C - DDR training initialization extended address */ + uint init_addr; /* 0x2148 - DDR training initialization address */ + uint init_ext_addr; /* 0x214C - DDR training initialization extended address */ char res8_1[16]; uint timing_cfg_4; /* 0x2160 - DDR SDRAM Timing Configuration Register 4 */ uint timing_cfg_5; /* 0x2164 - DDR SDRAM Timing Configuration Register 5 */ diff --git a/include/asm-ppc/immap_86xx.h b/include/asm-ppc/immap_86xx.h index 7526061d5a..0b78c94f7c 100644 --- a/include/asm-ppc/immap_86xx.h +++ b/include/asm-ppc/immap_86xx.h @@ -109,7 +109,7 @@ typedef struct ccsr_ddr { uint cs4_config; /* 0x2090 - DDR Chip Select Configuration */ uint cs5_config; /* 0x2094 - DDR Chip Select Configuration */ char res7[104]; - uint ext_refrec; /* 0x2100 - DDR SDRAM extended refresh recovery */ + uint timing_cfg_3; /* 0x2100 - DDR SDRAM Timing Configuration Register 3 */ uint timing_cfg_0; /* 0x2104 - DDR SDRAM Timing Configuration Register 0 */ uint timing_cfg_1; /* 0x2108 - DDR SDRAM Timing Configuration Register 1 */ uint timing_cfg_2; /* 0x210c - DDR SDRAM Timing Configuration Register 2 */ @@ -126,7 +126,7 @@ typedef struct ccsr_ddr { uint sdram_ocd_cntl; /* 0x2140 - DDR SDRAM OCD Control */ uint sdram_ocd_status; /* 0x2144 - DDR SDRAM OCD Status */ uint init_addr; /* 0x2148 - DDR training initialzation address */ - uint init_addr_ext; /* 0x214C - DDR training initialzation extended address */ + uint init_ext_addr; /* 0x214C - DDR training initialzation extended address */ char res10[2728]; uint ip_rev1; /* 0x2BF8 - DDR IP Block Revision 1 */ uint ip_rev2; /* 0x2BFC - DDR IP Block Revision 2 */ diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h index 9e70198e42..585411c4e2 100644 --- a/include/configs/MPC8610HPCD.h +++ b/include/configs/MPC8610HPCD.h @@ -114,7 +114,7 @@ #if 0 /* TODO */ #define CFG_DDR_CS0_BNDS 0x0000000F #define CFG_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */ -#define CFG_DDR_EXT_REFRESH 0x00000000 +#define CFG_DDR_TIMING_3 0x00000000 #define CFG_DDR_TIMING_0 0x00260802 #define CFG_DDR_TIMING_1 0x3935d322 #define CFG_DDR_TIMING_2 0x14904cc8 diff --git a/include/configs/katmai.h b/include/configs/katmai.h index 122b7006e1..d2f6b1021a 100644 --- a/include/configs/katmai.h +++ b/include/configs/katmai.h @@ -48,12 +48,8 @@ * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) *----------------------------------------------------------------------*/ -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CFG_MALLOC_LEN (512 * 1024) /* Reserve 512 kB for malloc */ - #define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ #define CFG_FLASH_BASE 0xff000000 /* start of FLASH */ -#define CFG_MONITOR_BASE TEXT_BASE #define CFG_PERIPHERAL_BASE 0xa0000000 /* internal peripherals */ #define CFG_ISRAM_BASE 0x90000000 /* internal SRAM */ @@ -82,6 +78,10 @@ #define CFG_ACE_BASE 0xfe000000 /* Xilinx ACE controller - Compact Flash */ +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_MONITOR_LEN (0xFFFFFFFF - CFG_MONITOR_LEN + 1) +#define CFG_MALLOC_LEN (512 * 1024) /* Reserve 512 kB for malloc */ + /*----------------------------------------------------------------------- * Initial RAM & stack pointer (placed in internal SRAM) *----------------------------------------------------------------------*/ diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index 690584a786..1f669aa8f6 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -91,9 +91,9 @@ /* Additional registers for watchdog timer post test */ -#define CFG_DSPIC_TEST_ADDR (CFG_PERIPHERAL_BASE + GPT0_MASK1) #define CFG_WATCHDOG_TIME_ADDR (CFG_PERIPHERAL_BASE + GPT0_MASK2) #define CFG_WATCHDOG_FLAGS_ADDR (CFG_PERIPHERAL_BASE + GPT0_MASK1) +#define CFG_DSPIC_TEST_ADDR CFG_WATCHDOG_FLAGS_ADDR #define CFG_WATCHDOG_MAGIC 0x12480000 #define CFG_WATCHDOG_MAGIC_MASK 0xFFFF0000 #define CFG_DSPIC_TEST_MASK 0x00000001 diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h index 18cedff929..20da73e0fa 100644 --- a/include/configs/sbc8641d.h +++ b/include/configs/sbc8641d.h @@ -136,7 +136,7 @@ #define CFG_DDR_CS1_CONFIG 0x00000000 #define CFG_DDR_CS2_CONFIG 0x00000000 #define CFG_DDR_CS3_CONFIG 0x00000000 - #define CFG_DDR_EXT_REFRESH 0x00000000 + #define CFG_DDR_TIMING_3 0x00000000 #define CFG_DDR_TIMING_0 0x00220802 #define CFG_DDR_TIMING_1 0x38377322 #define CFG_DDR_TIMING_2 0x002040c7 diff --git a/lib_ppc/cache.c b/lib_ppc/cache.c index 27e1a823c6..5bfb220707 100644 --- a/lib_ppc/cache.c +++ b/lib_ppc/cache.c @@ -23,6 +23,7 @@ #include <common.h> #include <asm/cache.h> +#include <watchdog.h> void flush_cache (ulong start_addr, ulong size) { @@ -35,6 +36,7 @@ void flush_cache (ulong start_addr, ulong size) addr < end_addr; addr += CFG_CACHELINE_SIZE) { asm ("dcbst 0,%0": :"r" (addr)); + WATCHDOG_RESET(); } asm ("sync"); /* Wait for all dcbst to complete on bus */ @@ -42,6 +44,7 @@ void flush_cache (ulong start_addr, ulong size) addr < end_addr; addr += CFG_CACHELINE_SIZE) { asm ("icbi 0,%0": :"r" (addr)); + WATCHDOG_RESET(); } } asm ("sync"); /* Always flush prefetch queue in any case */ diff --git a/post/board/lwmon/Makefile b/post/board/lwmon/Makefile index 899b0dc1f3..d2932bed13 100644 --- a/post/board/lwmon/Makefile +++ b/post/board/lwmon/Makefile @@ -20,10 +20,10 @@ # Foundation, Inc., 59 Temple Place, Suite 330, Boston, # MA 02111-1307 USA # - +include $(OBJTREE)/include/autoconf.mk LIB = libpostlwmon.a -COBJS = sysmon.o +COBJS-$(CONFIG_HAS_POST) += sysmon.o include $(TOPDIR)/post/rules.mk diff --git a/post/board/lwmon5/sysmon.c b/post/board/lwmon5/sysmon.c index 02d5f6f32a..793f670e24 100644 --- a/post/board/lwmon5/sysmon.c +++ b/post/board/lwmon5/sysmon.c @@ -32,9 +32,9 @@ * The test passes when all the following voltages and temperatures * are within allowed ranges: * - * Temperature -40 .. +85 C - * +5V +4.75 .. +5.25 V - * +5V standby +4.75 .. +5.25 V + * Temperature -40 .. +90 C + * +5V +4.50 .. +5.50 V + * +5V standby +3.50 .. +5.50 V * * LCD backlight is not enabled if temperature values are not within * allowed ranges (-30 .. + 80). The brightness of backlite can be @@ -60,6 +60,21 @@ extern int dspic_read(ushort reg); #define RELOC(x) if (x != NULL) x = (void *) ((ulong) (x) + gd->reloc_off) +#define REG_TEMPERATURE 0x12BC +#define REG_VOLTAGE_5V 0x12CA +#define REG_VOLTAGE_5V_STANDBY 0x12C6 + +#define TEMPERATURE_MIN (-40) /* degr. C */ +#define TEMPERATURE_MAX (+90) /* degr. C */ +#define TEMPERATURE_DISPLAY_MIN (-35) /* degr. C */ +#define TEMPERATURE_DISPLAY_MAX (+85) /* degr. C */ + +#define VOLTAGE_5V_MIN (+4500) /* mV */ +#define VOLTAGE_5V_MAX (+5500) /* mV */ + +#define VOLTAGE_5V_STANDBY_MIN (+3500) /* mV */ +#define VOLTAGE_5V_STANDBY_MAX (+5500) /* mV */ + typedef struct sysmon_s sysmon_t; typedef struct sysmon_table_s sysmon_table_t; @@ -107,17 +122,29 @@ struct sysmon_table_s static sysmon_table_t sysmon_table[] = { - {"Temperature", " C", &sysmon_dspic, NULL, sysmon_backlight_disable, - 1, 1, -32768, 32767, 0xFFFF, 0x8000-40, 0x8000+85, 0, - 0x8000-30, 0x8000+80, 0, 0x12BC}, - - {"+ 5 V", "V", &sysmon_dspic, NULL, NULL, - 100, 1000, -0x8000, 0x7FFF, 0xFFFF, 0x8000+4750, 0x8000+5250, 0, - 0x8000+4750, 0x8000+5250, 0, 0x12CA}, - - {"+ 5 V standby", "V", &sysmon_dspic, NULL, NULL, - 100, 1000, -0x8000, 0x7FFF, 0xFFFF, 0x8000+4750, 0x8000+5250, 0, - 0x8000+4750, 0x8000+5250, 0, 0x12C6}, + { + "Temperature", " C", &sysmon_dspic, NULL, sysmon_backlight_disable, + 1, 1, -32768, 32767, 0xFFFF, + 0x8000 + TEMPERATURE_MIN, 0x8000 + TEMPERATURE_MAX, 0, + 0x8000 + TEMPERATURE_DISPLAY_MIN, 0x8000 + TEMPERATURE_DISPLAY_MAX, 0, + REG_TEMPERATURE, + }, + + { + "+ 5 V", "V", &sysmon_dspic, NULL, NULL, + 100, 1000, 0, 0xFFFF, 0xFFFF, + VOLTAGE_5V_MIN, VOLTAGE_5V_MAX, 0, + VOLTAGE_5V_MIN, VOLTAGE_5V_MAX, 0, + REG_VOLTAGE_5V, + }, + + { + "+ 5 V standby", "V", &sysmon_dspic, NULL, NULL, + 100, 1000, 0, 0xFFFF, 0xFFFF, + VOLTAGE_5V_STANDBY_MIN, VOLTAGE_5V_STANDBY_MAX, 0, + VOLTAGE_5V_STANDBY_MIN, VOLTAGE_5V_STANDBY_MAX, 0, + REG_VOLTAGE_5V_STANDBY, + }, }; static int sysmon_table_size = sizeof(sysmon_table) / sizeof(sysmon_table[0]); diff --git a/post/board/lwmon5/watchdog.c b/post/board/lwmon5/watchdog.c index 16c01bee43..1246278a58 100644 --- a/post/board/lwmon5/watchdog.c +++ b/post/board/lwmon5/watchdog.c @@ -52,8 +52,9 @@ static void watchdog_magic_write(uint value) int sysmon1_post_test(int flags) { - if (gpio_read_in_bit(CFG_GPIO_SYSMON_STATUS)) { - /* 3.1. GPIO62 is low + if (gpio_read_in_bit(CFG_GPIO_SYSMON_STATUS) == 0) { + /* + * 3.1. GPIO62 is low * Assuming system voltage failure. */ post_log("Abnormal voltage detected (GPIO62)\n"); diff --git a/post/board/netta/Makefile b/post/board/netta/Makefile index 60c7790ace..8a8578f439 100644 --- a/post/board/netta/Makefile +++ b/post/board/netta/Makefile @@ -20,10 +20,10 @@ # Foundation, Inc., 59 Temple Place, Suite 330, Boston, # MA 02111-1307 USA # - +include $(OBJTREE)/include/autoconf.mk LIB = libpostnetta.a -COBJS = codec.o dsp.o +COBJS-$(CONFIG_HAS_POST) += codec.o dsp.o include $(TOPDIR)/post/rules.mk diff --git a/post/cpu/mpc8xx/Makefile b/post/cpu/mpc8xx/Makefile index f871cbab64..162924f6b2 100644 --- a/post/cpu/mpc8xx/Makefile +++ b/post/cpu/mpc8xx/Makefile @@ -20,10 +20,11 @@ # Foundation, Inc., 59 Temple Place, Suite 330, Boston, # MA 02111-1307 USA # +include $(OBJTREE)/include/autoconf.mk LIB = libpostmpc8xx.a -AOBJS = cache_8xx.o -COBJS = cache.o ether.o spr.o uart.o usb.o watchdog.o +AOBJS-$(CONFIG_HAS_POST) += cache_8xx.o +COBJS-$(CONFIG_HAS_POST) += cache.o ether.o spr.o uart.o usb.o watchdog.o include $(TOPDIR)/post/rules.mk diff --git a/tools/.gitignore b/tools/.gitignore index 979f2dac0d..df3500d965 100644 --- a/tools/.gitignore +++ b/tools/.gitignore @@ -15,3 +15,4 @@ /fdt_strerror.c /fdt_wip.c /libfdt_internal.h +/zlib.h |