diff options
Diffstat (limited to 'board/toradex/apalis_t30/apalis_t30.c')
| -rw-r--r-- | board/toradex/apalis_t30/apalis_t30.c | 71 |
1 files changed, 53 insertions, 18 deletions
diff --git a/board/toradex/apalis_t30/apalis_t30.c b/board/toradex/apalis_t30/apalis_t30.c index 773f9e9580..e91267b0b4 100644 --- a/board/toradex/apalis_t30/apalis_t30.c +++ b/board/toradex/apalis_t30/apalis_t30.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012-2016 Toradex, Inc. + * Copyright (c) 2012-2017 Toradex, Inc. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -13,6 +13,7 @@ #include <asm/io.h> #include <dm.h> #include <i2c.h> +#include <pci_tegra.h> #include "../common/tdx-common.h" #include "pinmux-config-apalis_t30.h" @@ -22,6 +23,13 @@ DECLARE_GLOBAL_DATA_PTR; #define PMU_I2C_ADDRESS 0x2D #define MAX_I2C_RETRY 3 +#ifdef CONFIG_APALIS_T30_PCIE_EVALBOARD_INIT +#define PEX_PERST_N TEGRA_GPIO(S, 7) /* Apalis GPIO7 */ +#define RESET_MOCI_CTRL TEGRA_GPIO(I, 4) + +static int pci_reset_status; +#endif /* CONFIG_APALIS_T30_PCIE_EVALBOARD_INIT */ + int arch_misc_init(void) { /* Default memory arguments */ @@ -127,25 +135,52 @@ int tegra_pcie_board_init(void) return err; } -#ifdef APALIS_T30_PCIE_EVALBOARD_INIT -#define PEX_PERST_N GPIO_PS7 /* Apalis GPIO7 */ -#define RESET_MOCI_N GPIO_PI4 - - /* Reset PLX PEX 8605 PCIe Switch plus PCIe devices on Apalis Evaluation - Board */ +#ifdef CONFIG_APALIS_T30_PCIE_EVALBOARD_INIT gpio_request(PEX_PERST_N, "PEX_PERST_N"); - gpio_request(RESET_MOCI_N, "RESET_MOCI_N"); - gpio_direction_output(PEX_PERST_N, 0); - gpio_direction_output(RESET_MOCI_N, 0); - /* Must be asserted for 100 ms after power and clocks are stable */ - mdelay(100); - gpio_set_value(PEX_PERST_N, 1); - /* Err_5: PEX_REFCLK_OUTpx/nx Clock Outputs is not Guaranteed Until - 900 us After PEX_PERST# De-assertion */ - mdelay(1); - gpio_set_value(RESET_MOCI_N, 1); -#endif /* APALIS_T30_PCIE_EVALBOARD_INIT */ + gpio_request(RESET_MOCI_CTRL, "RESET_MOCI_CTRL"); +#endif /* CONFIG_APALIS_T30_PCIE_EVALBOARD_INIT */ return 0; } + +void tegra_pcie_board_port_reset(struct tegra_pcie_port *port) +{ + int index = tegra_pcie_port_index_of_port(port); + if (index == 2) { /* I210 Gigabit Ethernet Controller (On-module) */ + tegra_pcie_port_reset(port); + } +#ifdef CONFIG_APALIS_T30_PCIE_EVALBOARD_INIT + /* + * Apalis PCIe aka port 1 and Apalis Type Specific 4 Lane PCIe aka port + * 0 share the same RESET_MOCI therefore only assert it once for both + * ports to avoid loosing the previously brought up port again. + */ + else if ((index == 1) || (index == 0)) { + /* only do it once per init cycle */ + if (pci_reset_status % 2 == 0) { + /* + * Reset PLX PEX 8605 PCIe Switch plus PCIe devices on + * Apalis Evaluation Board + */ + gpio_direction_output(PEX_PERST_N, 0); + gpio_direction_output(RESET_MOCI_CTRL, 0); + + /* + * Must be asserted for 100 ms after power and clocks + * are stable + */ + mdelay(100); + + gpio_set_value(PEX_PERST_N, 1); + /* + * Err_5: PEX_REFCLK_OUTpx/nx Clock Outputs is not + * Guaranteed Until 900 us After PEX_PERST# De-assertion + */ + mdelay(1); + gpio_set_value(RESET_MOCI_CTRL, 1); + } + pci_reset_status++; + } +#endif /* CONFIG_APALIS_T30_PCIE_EVALBOARD_INIT */ +} #endif /* CONFIG_PCI_TEGRA */ |