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Diffstat (limited to 'drivers/mtd')
-rw-r--r--drivers/mtd/nand/mxs_nand.c18
1 files changed, 17 insertions, 1 deletions
diff --git a/drivers/mtd/nand/mxs_nand.c b/drivers/mtd/nand/mxs_nand.c
index 42fb1877e5..43f00a5457 100644
--- a/drivers/mtd/nand/mxs_nand.c
+++ b/drivers/mtd/nand/mxs_nand.c
@@ -693,10 +693,12 @@ static int mxs_nand_ecc_read_page(struct mtd_info *mtd, struct nand_chip *nand,
{
struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
struct mxs_dma_desc *d;
+ struct mxs_bch_regs *bch_regs = (struct mxs_bch_regs *)MXS_BCH_BASE;
uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
uint32_t corrected = 0, failed = 0;
uint8_t *status;
int i, ret;
+ int flag = 0;
/* Compile the DMA descriptor - wait for ready. */
d = mxs_nand_get_dma_desc(nand_info);
@@ -800,8 +802,13 @@ static int mxs_nand_ecc_read_page(struct mtd_info *mtd, struct nand_chip *nand,
if (status[i] == 0x00)
continue;
- if (status[i] == 0xff)
+ if (status[i] == 0xff) {
+ if (is_mx6dqp() || is_soc_type(MXC_SOC_MX7) ||
+ is_cpu_type(MXC_CPU_MX6UL))
+ if (readl(bch_regs->hw_bch_debug1))
+ flag = 1;
continue;
+ }
if (status[i] == 0xfe) {
if (mxs_nand_erased_page(mtd, nand,
@@ -833,6 +840,9 @@ static int mxs_nand_ecc_read_page(struct mtd_info *mtd, struct nand_chip *nand,
memcpy(buf, nand_info->data_buf, mtd->writesize);
+ if (flag)
+ memset(buf, 0xff, mtd->writesize);
+
rtn:
mxs_nand_return_dma_descs(nand_info);
@@ -1155,6 +1165,12 @@ static int mxs_nand_scan_bbt(struct mtd_info *mtd)
BCH_FLASHLAYOUT1_GF13_0_GF14_1_OFFSET;
writel(tmp, &bch_regs->hw_bch_flash0layout1);
+ /* Set erase threshold to ecc strength for mx6ul, mx6qp and mx7 */
+ if (is_mx6dqp() || is_soc_type(MXC_SOC_MX7) ||
+ is_cpu_type(MXC_CPU_MX6UL))
+ writel(BCH_MODE_ERASE_THRESHOLD(ecc_strength),
+ &bch_regs->hw_bch_mode);
+
/* Set *all* chip selects to use layout 0 */
writel(0, &bch_regs->hw_bch_layoutselect);