From f1b05a9ea48a15fcbfba067d5b2320c4159d5302 Mon Sep 17 00:00:00 2001 From: Max Krummenacher Date: Wed, 12 Feb 2020 20:15:34 +0100 Subject: verdin-imx8mm.c: set eth phy skew Set the Ethernet PHY's RGMII skew registers according to the needed skew. Related-to: ELB-1970 Signed-off-by: Max Krummenacher --- board/toradex/verdin-imx8mm/verdin-imx8mm.c | 33 ++++++++++++++++++++--------- 1 file changed, 23 insertions(+), 10 deletions(-) diff --git a/board/toradex/verdin-imx8mm/verdin-imx8mm.c b/board/toradex/verdin-imx8mm/verdin-imx8mm.c index e3c5774410..1edae1e545 100644 --- a/board/toradex/verdin-imx8mm/verdin-imx8mm.c +++ b/board/toradex/verdin-imx8mm/verdin-imx8mm.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -99,16 +100,28 @@ static int setup_fec(void) int board_phy_config(struct phy_device *phydev) { - /* TODO: check settings for KSZ9030/31 */ - - /* enable rgmii rxc skew and phy mode select to RGMII copper */ - phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); - phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); - - phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00); - phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee); - phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); - phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); +/* + * The PHY adds 1.2ns for the RXC and 0ns for TXC clock by default. The MAC + * and the layout don't add a skew between clock and data. + * Add 0.3ns for the RXC path and 0.96 + 0.42 ns (1.38 ns) for the TXC path + * to get the required clock skews. + */ + /* control data pad skew - devaddr = 0x02, register = 0x04 */ + ksz9031_phy_extended_write(phydev, 0x02, + MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW, + MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0070); + /* rx data pad skew - devaddr = 0x02, register = 0x05 */ + ksz9031_phy_extended_write(phydev, 0x02, + MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW, + MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x7777); + /* tx data pad skew - devaddr = 0x02, register = 0x06 */ + ksz9031_phy_extended_write(phydev, 0x02, + MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW, + MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000); + /* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */ + ksz9031_phy_extended_write(phydev, 0x02, + MII_KSZ9031_EXT_RGMII_CLOCK_SKEW, + MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03f4); if (phydev->drv->config) phydev->drv->config(phydev); -- cgit v1.2.3