From fc0717dc30824a3e0b9115c44787af7483e5aaa7 Mon Sep 17 00:00:00 2001 From: Justin Waters Date: Wed, 30 Apr 2008 16:40:21 -0400 Subject: Add support for AT91SAM9G20-EK This patch adds support for the AT91SAM9G20-EK board. It comes from the patch u-boot-1.1.5_atmel_1.6.diff, courtesy of linux4sam.org. Signed-off-by: Justin Waters --- Makefile | 3 + board/at91sam9260ek/at91sam9260ek.c | 6 +- board/at91sam9g20ek/Makefile | 46 +++++ board/at91sam9g20ek/at91sam9g20ek.c | 198 ++++++++++++++++++ board/at91sam9g20ek/config.mk | 1 + board/at91sam9g20ek/dm9161a.c | 301 ++++++++++++++++++++++++++++ board/at91sam9g20ek/nand.c | 107 ++++++++++ board/at91sam9g20ek/u-boot.lds | 55 +++++ doc/README.SBC8560 | 57 ------ include/asm-arm/arch-at91sam926x/hardware.h | 2 +- include/asm-arm/mach-types.h | 13 ++ include/configs/at91sam9g20ek.h | 241 ++++++++++++++++++++++ 12 files changed, 971 insertions(+), 59 deletions(-) create mode 100644 board/at91sam9g20ek/Makefile create mode 100644 board/at91sam9g20ek/at91sam9g20ek.c create mode 100644 board/at91sam9g20ek/config.mk create mode 100644 board/at91sam9g20ek/dm9161a.c create mode 100644 board/at91sam9g20ek/nand.c create mode 100644 board/at91sam9g20ek/u-boot.lds delete mode 100644 doc/README.SBC8560 create mode 100644 include/configs/at91sam9g20ek.h diff --git a/Makefile b/Makefile index 949eae6aa3..ce2050f0ca 100644 --- a/Makefile +++ b/Makefile @@ -2020,6 +2020,9 @@ at91sam9260ek_config : unconfig at91sam9xeek_config : unconfig @./mkconfig -n at91sam9xeek at91sam9260ek arm arm926ejs at91sam9260ek NULL at91sam926x +at91sam9g20ek_config : unconfig + @./mkconfig $(@:_config=) arm arm926ejs at91sam9g20ek NULL at91sam926x + at91sam9261ek_config : unconfig @./mkconfig $(@:_config=) arm arm926ejs at91sam9261ek NULL at91sam926x diff --git a/board/at91sam9260ek/at91sam9260ek.c b/board/at91sam9260ek/at91sam9260ek.c index 5fce346a25..410c7e2aa1 100644 --- a/board/at91sam9260ek/at91sam9260ek.c +++ b/board/at91sam9260ek/at91sam9260ek.c @@ -137,7 +137,7 @@ int AT91F_EMAC_Hardware_Init(void) AT91C_BASE_PIOA->PIO_PPUDR = AT91C_PA14_ERX0 | AT91C_PA15_ERX1 | AT91C_PA17_ERXDV | AT91C_PA25_ERX2 | AT91C_PA26_ERX3 | AT91C_PA28_ECRS; - + /* Need to reset PHY -> 500ms reset */ AT91C_BASE_RSTC->RSTC_RMR = (AT91C_RSTC_KEY & ((unsigned int)0xA5<<24)) | (AT91C_RSTC_ERSTL & (0x0D << 8)) | AT91C_RSTC_URSTEN; @@ -147,6 +147,10 @@ int AT91F_EMAC_Hardware_Init(void) /* Wait for end hardware reset */ while (!(AT91C_BASE_RSTC->RSTC_RSR & AT91C_RSTC_NRSTL)); + /* Resore NRST value */ + AT91C_BASE_RSTC->RSTC_RMR = (AT91C_RSTC_KEY & ((unsigned int)0xA5<<24)) | + (AT91C_RSTC_ERSTL & (0x0 << 8)) | AT91C_RSTC_URSTEN; + /* Re-enable pull-up */ AT91C_BASE_PIOA->PIO_PPUER = AT91C_PA14_ERX0 | AT91C_PA15_ERX1 | AT91C_PA17_ERXDV | AT91C_PA25_ERX2 | diff --git a/board/at91sam9g20ek/Makefile b/board/at91sam9g20ek/Makefile new file mode 100644 index 0000000000..8028d5d1ad --- /dev/null +++ b/board/at91sam9g20ek/Makefile @@ -0,0 +1,46 @@ +# +# (C) Copyright 2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := at91sam9g20ek.o dm9161a.o nand.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/at91sam9g20ek/at91sam9g20ek.c b/board/at91sam9g20ek/at91sam9g20ek.c new file mode 100644 index 0000000000..1cd71fb314 --- /dev/null +++ b/board/at91sam9g20ek/at91sam9g20ek.c @@ -0,0 +1,198 @@ +/* + * (C) Copyright 2008 + * ATMEL Corporation + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#include + +/* ------------------------------------------------------------------------- */ +/* + * Miscelaneous platform dependent initialisations + */ + +int board_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + /* Enable Ctrlc */ + console_init_f (); + + /* Enable clocks for SMC */ + AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_SYS; + + /* memory and cpu-speed are setup before relocation */ + /* so we do _nothing_ here */ + + /* arch number of AT91SAM9G20EK-Board */ + gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9G20EK; + /* adress of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + return 0; +} + + +int dram_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_dram[0].start = PHYS_SDRAM; + gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; + return 0; +} + + +int board_late_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + /* Fix Ethernet Initialization Bug when starting Linux from U-Boot */ +#if (CONFIG_COMMANDS & CFG_CMD_NET) + eth_init(gd->bd); +#endif + + return 0; +} + + + +int AT91F_Serial_Hardware_Init(void) +{ + +/* DBGU */ +#ifdef CONFIG_DBGU + *AT91C_PIOB_PDR = AT91C_PB15_DTXD | AT91C_PB14_DRXD; /* PB 15 & 15 */ + *AT91C_PMC_PCER = 1 << AT91C_ID_SYS; /* enable clock */ +#endif + +/* USART 0 */ +#ifdef CONFIG_USART0 + *AT91C_PIOB_PDR = AT91C_PB4_TXD0 | AT91C_PB5_RXD0; /* PB 4 & 5 */ + *AT91C_PMC_PCER |= 1 << AT91C_ID_US0; /* enable clock */ +#endif + +#ifdef CONFIG_USART1 + *AT91C_PIOB_PDR = AT91C_PB6_TXD1 | AT91C_PB7_RXD1; /* PB 6 & 7 */ + *AT91C_PMC_PCER |= 1 << AT91C_ID_US1; /* enable clock */ +#endif + +#ifdef CONFIG_USART2 + *AT91C_PIOB_PDR = AT91C_PB8_TXD2 | AT91C_PB9_RXD2; /* PB 8 & 9 */ + *AT91C_PMC_PCER |= 1 << AT91C_ID_US2; /* enable clock */ +#endif +} + + +#ifdef CONFIG_DRIVER_ETHER +#if (CONFIG_COMMANDS & CFG_CMD_NET) + +extern AT91PS_EMAC p_mac; + +int AT91F_EMAC_Hardware_Init(void) +{ + unsigned int periphAEnable, periphBEnable; + unsigned int val, i; + int ret; + + p_mac = AT91C_BASE_EMACB; + + /* Disable pull-up on: + RXDV (PA17) => PHY normal mode (not Test mode) + + ERX0 (PA14) => PHY ADDR0 + ERX1 (PA15) => PHY ADDR1 + ERX2 (PA25) => PHY ADDR2 + ERX3 (PA26) => PHY ADDR3 + ECRS (PA28) => PHY ADDR4 => PHYADDR = 0x0 + + PHY has internal pull-down + */ + + AT91C_BASE_PIOA->PIO_PPUDR = AT91C_PA14_ERX0 | AT91C_PA15_ERX1 | + AT91C_PA17_ERXDV | AT91C_PA25_ERX2 | + AT91C_PA26_ERX3 | AT91C_PA28_ECRS; + + /* Need to reset PHY -> 500ms reset */ + AT91C_BASE_RSTC->RSTC_RMR = (AT91C_RSTC_KEY & ((unsigned int)0xA5<<24)) | + (AT91C_RSTC_ERSTL & (0x0D << 8)) | AT91C_RSTC_URSTEN; + AT91C_BASE_RSTC->RSTC_RCR = (AT91C_RSTC_KEY & ((unsigned int)0xA5<<24)) | + AT91C_RSTC_EXTRST; + + /* Wait for end hardware reset */ + while (!(AT91C_BASE_RSTC->RSTC_RSR & AT91C_RSTC_NRSTL)); + + /* Resore NRST value */ + AT91C_BASE_RSTC->RSTC_RMR = (AT91C_RSTC_KEY & ((unsigned int)0xA5<<24)) | + (AT91C_RSTC_ERSTL & (0x0 << 8)) | AT91C_RSTC_URSTEN; + + /* Re-enable pull-up */ + AT91C_BASE_PIOA->PIO_PPUER = AT91C_PA14_ERX0 | AT91C_PA15_ERX1 | + AT91C_PA17_ERXDV | AT91C_PA25_ERX2 | + AT91C_PA26_ERX3 | AT91C_PA28_ECRS; + +#ifdef CONFIG_AT91C_USE_RMII + periphAEnable = ((unsigned int) AT91C_PA21_EMDIO ) | + ((unsigned int) AT91C_PA20_EMDC ) | + ((unsigned int) AT91C_PA19_ETXCK ) | + ((unsigned int) AT91C_PA18_ERXER ) | + ((unsigned int) AT91C_PA14_ERX0 ) | + ((unsigned int) AT91C_PA17_ERXDV ) | + ((unsigned int) AT91C_PA15_ERX1 ) | + ((unsigned int) AT91C_PA16_ETXEN ) | + ((unsigned int) AT91C_PA12_ETX0 ) | + ((unsigned int) AT91C_PA13_ETX1 ); + + periphBEnable = 0; +#else + periphAEnable = ((unsigned int) AT91C_PA21_EMDIO ) | + ((unsigned int) AT91C_PA19_ETXCK ) | + ((unsigned int) AT91C_PA20_EMDC ) | + ((unsigned int) AT91C_PA18_ERXER ) | + ((unsigned int) AT91C_PA14_ERX0 ) | + ((unsigned int) AT91C_PA17_ERXDV ) | + ((unsigned int) AT91C_PA15_ERX1 ) | + ((unsigned int) AT91C_PA16_ETXEN ) | + ((unsigned int) AT91C_PA12_ETX0 ) | + ((unsigned int) AT91C_PA13_ETX1 ); + + periphBEnable = ((unsigned int) AT91C_PA27_ERXCK ) | + ((unsigned int) AT91C_PA29_ECOL ) | + ((unsigned int) AT91C_PA25_ERX2 ) | + ((unsigned int) AT91C_PA26_ERX3 ) | + ((unsigned int) AT91C_PA22_ETXER ) | + ((unsigned int) AT91C_PA10_ETX2 ) | + ((unsigned int) AT91C_PA11_ETX3 ) | + ((unsigned int) AT91C_PA28_ECRS ); +#endif + AT91C_BASE_PIOA->PIO_ASR = periphAEnable; + AT91C_BASE_PIOA->PIO_BSR = periphBEnable; + AT91C_BASE_PIOA->PIO_PDR = (periphAEnable | periphBEnable); +} + +#endif /* CONFIG_COMMANDS & CFG_CMD_NET */ +#endif /* CONFIG_DRIVER_ETHER */ diff --git a/board/at91sam9g20ek/config.mk b/board/at91sam9g20ek/config.mk new file mode 100644 index 0000000000..ff2cfd170b --- /dev/null +++ b/board/at91sam9g20ek/config.mk @@ -0,0 +1 @@ +TEXT_BASE = 0x23f00000 diff --git a/board/at91sam9g20ek/dm9161a.c b/board/at91sam9g20ek/dm9161a.c new file mode 100644 index 0000000000..cd9933e902 --- /dev/null +++ b/board/at91sam9g20ek/dm9161a.c @@ -0,0 +1,301 @@ +/* + * (C) Copyright 2003 + * Author : Hamid Ikdoumi (Atmel) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#ifdef CONFIG_DRIVER_ETHER + +#if (CONFIG_COMMANDS & CFG_CMD_NET) + +/* + * Name: + * dm9161a_IsPhyConnected + * Description: + * Reads the 2 PHY ID registers + * Arguments: + * p_mac - pointer to AT91S_EMAC struct + * Return value: + * TRUE - if id read successfully + * FALSE- if error + */ +static unsigned int dm9161a_IsPhyConnected (AT91PS_EMAC p_mac) +{ + unsigned short Id1, Id2; + + at91_EmacEnableMDIO (p_mac); + at91_EmacReadPhy (p_mac, SAM9260EK_PHY_ADDRESS, DM9161_PHYID1, &Id1); + at91_EmacReadPhy (p_mac, SAM9260EK_PHY_ADDRESS, DM9161_PHYID2, &Id2); + at91_EmacDisableMDIO (p_mac); + + if ((Id1 == (DM9161_PHYID1_OUI >> 6)) && + ((Id2 >> 10) == (DM9161_PHYID1_OUI & DM9161_LSB_MASK))) { + printf("DM9161A PHY Detected\n\r"); + return TRUE; + } + + return FALSE; +} + +/* + * Name: + * dm9161a_GetLinkSpeed + * Description: + * Link parallel detection status of MAC is checked and set in the + * MAC configuration registers + * Arguments: + * p_mac - pointer to MAC + * Return value: + * TRUE - if link status set succesfully + * FALSE - if link status not set + */ +static uchar dm9161a_GetLinkSpeed (AT91PS_EMAC p_mac) +{ + unsigned short stat1, stat2; + + if (!at91_EmacReadPhy (p_mac, SAM9260EK_PHY_ADDRESS, DM9161_BMSR, &stat1)) + return FALSE; + + if (!(stat1 & DM9161_LINK_STATUS)) /* link status up? */ + return FALSE; + + if (!at91_EmacReadPhy (p_mac, SAM9260EK_PHY_ADDRESS, DM9161_DSCSR, &stat2)) + return FALSE; + + if ((stat1 & DM9161_100BASE_TX_FD) && (stat2 & DM9161_100FDX)) { + /*set Emac for 100BaseTX and Full Duplex */ + p_mac->EMAC_NCFGR |= AT91C_EMAC_SPD | AT91C_EMAC_FD; + return TRUE; + } + + if ((stat1 & DM9161_10BASE_T_FD) && (stat2 & DM9161_10FDX)) { + /*set MII for 10BaseT and Full Duplex */ + p_mac->EMAC_NCFGR = (p_mac->EMAC_NCFGR & + ~(AT91C_EMAC_SPD | AT91C_EMAC_FD)) + | AT91C_EMAC_FD; + return TRUE; + } + + if ((stat1 & DM9161_100BASE_T4_HD) && (stat2 & DM9161_100HDX)) { + /*set MII for 100BaseTX and Half Duplex */ + p_mac->EMAC_NCFGR = (p_mac->EMAC_NCFGR & + ~(AT91C_EMAC_SPD | AT91C_EMAC_FD)) + | AT91C_EMAC_SPD; + return TRUE; + } + + if ((stat1 & DM9161_10BASE_T_HD) && (stat2 & DM9161_10HDX)) { + /*set MII for 10BaseT and Half Duplex */ + p_mac->EMAC_NCFGR &= ~(AT91C_EMAC_SPD | AT91C_EMAC_FD); + return TRUE; + } + + return FALSE; +} + + +/* + * Name: + * dm9161a_ResetPhy + * Description: + * Resets PHY + * Arguments: + * p_mac - pointer to struct AT91S_EMAC + * Return value: + * TRUE - if link status set succesfully + * FALSE - if link status not set + */ +static uchar dm9161a_ResetPhy(AT91PS_EMAC p_mac) +{ + unsigned short bmcr; + int timeout = 100; + uchar ret = TRUE; + + + bmcr = DM9161_RESET; + at91_EmacEnableMDIO (p_mac); + at91_EmacWritePhy (p_mac, SAM9260EK_PHY_ADDRESS, DM9161_BMCR, &bmcr); + + do { + at91_EmacReadPhy (p_mac, SAM9260EK_PHY_ADDRESS, DM9161_BMCR, &bmcr); + at91_EmacReadPhy (p_mac, SAM9260EK_PHY_ADDRESS, DM9161_BMCR, &bmcr); + timeout--; + } while ((bmcr & DM9161_RESET) && timeout); + + at91_EmacDisableMDIO (p_mac); + + if (!timeout) + ret = FALSE; + + return ret; +} + + +/* + * Name: + * dm9161a_InitPhy + * Description: + * MAC starts checking its link by using parallel detection and + * Autonegotiation and the same is set in the MAC configuration registers + * Arguments: + * p_mac - pointer to struct AT91S_EMAC + * Return value: + * TRUE - if link status set succesfully + * FALSE - if link status not set + */ +static uchar dm9161a_InitPhy (AT91PS_EMAC p_mac) +{ + unsigned int tick = 0; + unsigned short IntValue; + uchar ret = TRUE; + + at91_EmacEnableMDIO (p_mac); + + do { + /* Link status is latched, so read twice to get current value */ + at91_EmacReadPhy(p_mac, SAM9260EK_PHY_ADDRESS, DM9161_BMSR, &IntValue); + at91_EmacReadPhy(p_mac, SAM9260EK_PHY_ADDRESS, DM9161_BMSR, &IntValue); + + tick++; + } while (!(IntValue & DM9161_LINK_STATUS) && (tick < AT91C_ETH_TIMEOUT)); + + if (!(IntValue & DM9161_LINK_STATUS)){ + at91_EmacDisableMDIO (p_mac); + printf ("No link\n\r"); + ret = FALSE; + return ret; + } + + if (!dm9161a_GetLinkSpeed (p_mac)) { + /* Try another time */ + ret = dm9161a_GetLinkSpeed (p_mac); + } + + /* Disable PHY Interrupts */ + at91_EmacReadPhy (p_mac, SAM9260EK_PHY_ADDRESS, DM9161_MDINTR, &IntValue); + /* clear FDX, SPD, Link, INTR masks */ + IntValue &= ~(DM9161_FDX_MASK | DM9161_SPD_MASK | + DM9161_LINK_MASK | DM9161_INTR_MASK); + at91_EmacWritePhy (p_mac, SAM9260EK_PHY_ADDRESS, DM9161_MDINTR, &IntValue); + at91_EmacDisableMDIO (p_mac); + + return (ret); +} + + +/* + * Name: + * dm9161a_AutoNegotiate + * Description: + * MAC Autonegotiates with the partner status of same is set in the + * MAC configuration registers + * Arguments: + * dev - pointer to struct net_device + * Return value: + * TRUE - if link status set successfully + * FALSE - if link status not set + */ +static uchar dm9161a_AutoNegotiate (AT91PS_EMAC p_mac, int *status) +{ + unsigned short value; + unsigned short PhyAnar; + unsigned short PhyAnalpar; + + /* Set dm9161 control register */ + if (!at91_EmacReadPhy (p_mac, SAM9260EK_PHY_ADDRESS, DM9161_BMCR, &value)) + return FALSE; + value &= ~DM9161_AUTONEG; /* remove autonegotiation enable */ + value |= DM9161_ISOLATE; /* Electrically isolate PHY */ + if (!at91_EmacWritePhy (p_mac, SAM9260EK_PHY_ADDRESS, DM9161_BMCR, &value)) + return FALSE; + + /* Set the Auto_negotiation Advertisement Register */ + /* MII advertising for Next page, 100BaseTxFD and HD, 10BaseTFD and HD, IEEE 802.3 */ + PhyAnar = DM9161_NP | DM9161_TX_FDX | DM9161_TX_HDX | + DM9161_10_FDX | DM9161_10_HDX | DM9161_AN_IEEE_802_3; + if (!at91_EmacWritePhy (p_mac, SAM9260EK_PHY_ADDRESS, DM9161_ANAR, &PhyAnar)) + return FALSE; + + /* Read the Control Register */ + if (!at91_EmacReadPhy (p_mac, SAM9260EK_PHY_ADDRESS, DM9161_BMCR, &value)) + return FALSE; + + value |= DM9161_SPEED_SELECT | DM9161_AUTONEG | DM9161_DUPLEX_MODE; + if (!at91_EmacWritePhy (p_mac, SAM9260EK_PHY_ADDRESS, DM9161_BMCR, &value)) + return FALSE; + /* Restart Auto_negotiation */ + value |= DM9161_RESTART_AUTONEG; + if (!at91_EmacWritePhy (p_mac, SAM9260EK_PHY_ADDRESS, DM9161_BMCR, &value)) + return FALSE; + + /*check AutoNegotiate complete */ + udelay (10000); + at91_EmacReadPhy (p_mac, SAM9260EK_PHY_ADDRESS, DM9161_BMSR, &value); + if (!(value & DM9161_AUTONEG_COMP)) + return FALSE; + + /* Get the AutoNeg Link partner base page */ + if (!at91_EmacReadPhy (p_mac, SAM9260EK_PHY_ADDRESS, DM9161_ANLPAR, &PhyAnalpar)) + return FALSE; + + if ((PhyAnar & DM9161_TX_FDX) && (PhyAnalpar & DM9161_TX_FDX)) { + /*set MII for 100BaseTX and Full Duplex */ + p_mac->EMAC_NCFGR |= AT91C_EMAC_SPD | AT91C_EMAC_FD; + return TRUE; + } + + if ((PhyAnar & DM9161_10_FDX) && (PhyAnalpar & DM9161_10_FDX)) { + /*set MII for 10BaseT and Full Duplex */ + p_mac->EMAC_NCFGR = (p_mac->EMAC_NCFGR & + ~(AT91C_EMAC_SPD | AT91C_EMAC_FD)) + | AT91C_EMAC_FD; + return TRUE; + } + return FALSE; +} + + +/* + * Name: + * at91_GetPhyInterface + * Description: + * Initialise the interface functions to the PHY + * Arguments: + * None + * Return value: + * None + */ +void at91_GetPhyInterface(AT91PS_PhyOps p_phyops) +{ + p_phyops->Init = dm9161a_InitPhy; + p_phyops->IsPhyConnected = dm9161a_IsPhyConnected; + p_phyops->GetLinkSpeed = dm9161a_GetLinkSpeed; + p_phyops->AutoNegotiate = dm9161a_AutoNegotiate; + p_phyops->Reset = dm9161a_ResetPhy; +} + +#endif /* CONFIG_COMMANDS & CFG_CMD_NET */ + +#endif /* CONFIG_DRIVER_ETHER */ + diff --git a/board/at91sam9g20ek/nand.c b/board/at91sam9g20ek/nand.c new file mode 100644 index 0000000000..2a339a9ed7 --- /dev/null +++ b/board/at91sam9g20ek/nand.c @@ -0,0 +1,107 @@ +/* + * (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) + +#include + +/* + * hardware specific access to control-lines + */ +#define MASK_ALE (1 << 21) /* our ALE is AD21 */ +#define MASK_CLE (1 << 22) /* our CLE is AD22 */ + +/* + * Disk On Chip (NAND) Millenium initialization. + * The NAND lives in the CS3 space + */ +void at91sam9260ek_nand_init (struct nand_chip *nand) +{ + /* Setup Smart Media, first enable the address range of CS3 in HMATRIX user interface */ + AT91C_BASE_CCFG->CCFG_EBICSA |= AT91C_EBI_CS3A_SM; + + /* Configure SMC CS3 */ + AT91C_BASE_SMC->SMC_SETUP3 = (AT91C_SM_NWE_SETUP | AT91C_SM_NCS_WR_SETUP | + AT91C_SM_NRD_SETUP | AT91C_SM_NCS_RD_SETUP); + + AT91C_BASE_SMC->SMC_PULSE3 = (AT91C_SM_NWE_PULSE | AT91C_SM_NCS_WR_PULSE | AT91C_SM_NRD_PULSE | AT91C_SM_NCS_RD_PULSE); + + AT91C_BASE_SMC->SMC_CYCLE3 = (AT91C_SM_NWE_CYCLE | AT91C_SM_NRD_CYCLE); + + if ((nand->options & NAND_BUSWIDTH_16) == NAND_BUSWIDTH_16) + { + AT91C_BASE_SMC->SMC_CTRL3 = (AT91C_SMC_READMODE | AT91C_SMC_WRITEMODE | AT91C_SMC_NWAITM_NWAIT_DISABLE | + AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS | AT91C_SM_TDF); + } else { + AT91C_BASE_SMC->SMC_CTRL3 = (AT91C_SMC_READMODE | AT91C_SMC_WRITEMODE | AT91C_SMC_NWAITM_NWAIT_DISABLE | + AT91C_SMC_DBW_WIDTH_EIGTH_BITS | AT91C_SM_TDF); + } + + /* Configure RDY/BSY input signal */ + AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOC; + + AT91C_BASE_PIOC->PIO_ODR = AT91C_PIO_PC13; + AT91C_BASE_PIOC->PIO_PER = AT91C_PIO_PC13; + + AT91C_BASE_PIOC->PIO_PPUER = AT91C_PIO_PC13; /* Enable pull-up */ + + /* Enable NandFlash */ + AT91C_BASE_PIOC->PIO_PER = AT91C_PIO_PC14; + AT91C_BASE_PIOC->PIO_OER = AT91C_PIO_PC14; +} + +static void at91sam9260ek_nand_hwcontrol(struct mtd_info *mtd, int cmd) +{ + struct nand_chip *this = mtd->priv; + ulong IO_ADDR_W = (ulong) this->IO_ADDR_W; + + IO_ADDR_W &= ~(MASK_ALE|MASK_CLE); + switch (cmd) { + case NAND_CTL_SETCLE: IO_ADDR_W |= MASK_CLE; break; + case NAND_CTL_SETALE: IO_ADDR_W |= MASK_ALE; break; + case NAND_CTL_CLRNCE: *AT91C_PIOC_SODR = AT91C_PIO_PC14; break; + case NAND_CTL_SETNCE: *AT91C_PIOC_CODR = AT91C_PIO_PC14; break; + } + this->IO_ADDR_W = (void *) IO_ADDR_W; +} + +/* + * chip R/B detection + */ +static int at91sam9260ek_nand_ready(struct mtd_info *mtd) +{ + return (*AT91C_PIOC_PDSR & AT91C_PIO_PC13); +} + +void board_nand_init(struct nand_chip *nand) +{ + nand->eccmode = NAND_ECC_SOFT; + nand->hwcontrol = at91sam9260ek_nand_hwcontrol; + nand->dev_ready = at91sam9260ek_nand_ready; + nand->chip_delay = 18; + + at91sam9260ek_nand_init(nand); +} +#endif diff --git a/board/at91sam9g20ek/u-boot.lds b/board/at91sam9g20ek/u-boot.lds new file mode 100644 index 0000000000..d965a03813 --- /dev/null +++ b/board/at91sam9g20ek/u-boot.lds @@ -0,0 +1,55 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/doc/README.SBC8560 b/doc/README.SBC8560 deleted file mode 100644 index c4b642236e..0000000000 --- a/doc/README.SBC8560 +++ /dev/null @@ -1,57 +0,0 @@ -The port was tested on Wind River System Sbc8560 board -. U-Boot was installed on the flash memory of the -CPU card (no the SODIMM). - -NOTE: Please configure uboot compile to the proper PCI frequency and -setup the appropriate DIP switch settings. - -SBC8560 board: - -Make sure boards switches are set to their appropriate conditions. -Refer to the Engineering Reference Guide ERG-00300-002. Of particular -importance are: 1) the settings for JP4 (JP4 1-3 and 2-4), which -select the on-board FLASH device (Intel 28F128Jx); 2) The settings -for the Clock SW9 (33 MHz or 66 MHz). - - Note: SW9 Settings: 66 MHz - 4:1 ratio CCB clocks:SYSCLK - 3:1 ration e500 Core:CCB - pos1 - on, pos2 - on, pos3 - off, pos4 - on, pos5 - off, pos6 - on - Note: SW9 Settings: 33 MHz - 8:1 ratio CCB clocks:SYSCLK - 3:1 ration e500 Core:CCB - pos1 - on, pos2 - on, pos3 - on, pos4 - off, pos5 - off, pos6 - on - - -Flashing the FLASH device with the "Wind River ICE": - -1) Properly connect and configure the Wind River ICE to the target - JTAG port. This includes running the SBC8560 register script. Make - sure target memory can be read and written. - -2) Build the u-boot image: - make distclean - make SBC8560_66_config or SBC8560_33_config - make CROSS_COMPILE=.../ELDK3.0/ppc_8xx-/ all - - Note: reference is made to the ELDK3.0 compiler. Further, it seems - the ppc_8xx compiler is required for the 85xx (no 85xx - designated compiler in ELDK3.0) - -3) Convert the uboot (.elf) file to a uboot.bin file (using - visionClick converter). The bin file should be converted from - fffc0000 to ffffffff - -4) Setup the Flash Utility (tools menu) for: - - Do a "dc clr" [visionClick] to load the default register settings - Determine the clock speed of the PCI bus and set SW9 accordingly - Note: the speed of the PCI bus defaults to the slowest PCI card - PlayBack the "default" register file for the SBC8560 - Select the uboot.bin file with zero bias - Select the initialize Target prior to programming - Select the V28F640Jx (8192 x 8) 1 device FLASH Algorithm - Select the erase base address from FFFC0000 to FFFFFFFF - Select the start address from 0 with size of 4000 - -5) Erase and Program diff --git a/include/asm-arm/arch-at91sam926x/hardware.h b/include/asm-arm/arch-at91sam926x/hardware.h index ff5b3246f2..044acd26fe 100644 --- a/include/asm-arm/arch-at91sam926x/hardware.h +++ b/include/asm-arm/arch-at91sam926x/hardware.h @@ -23,7 +23,7 @@ #include -#ifdef CONFIG_AT91SAM9260EK +#if defined(CONFIG_AT91SAM9260EK) || defined(CONFIG_AT91SAM9G20EK) #ifndef __ASSEMBLY__ #include #else diff --git a/include/asm-arm/mach-types.h b/include/asm-arm/mach-types.h index 5fd67438b4..c32923200e 100644 --- a/include/asm-arm/mach-types.h +++ b/include/asm-arm/mach-types.h @@ -741,6 +741,7 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_AT91SAM9260EK 1099 #define MACH_TYPE_AT91SAM9263EK 1202 #define MACH_TYPE_AT91SAM9RLEK 1326 +#define MACH_TYPE_AT91SAM9G20EK 1624 #ifdef CONFIG_ARCH_EBSA110 # ifdef machine_arch_type @@ -9454,6 +9455,18 @@ extern unsigned int __machine_arch_type; # define machine_is_at91sam9rlek() (0) #endif +#ifdef CONFIG_MACH_AT91SAM9G20EK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT91SAM9G20EK +# endif +# define machine_is_at91sam9g20ek() (machine_arch_type == MACH_TYPE_AT91SAM9G20EK) +#else +# define machine_is_at91sam9g20ek() (0) +#endif + /* * These have not yet been registered */ diff --git a/include/configs/at91sam9g20ek.h b/include/configs/at91sam9g20ek.h new file mode 100644 index 0000000000..306f294083 --- /dev/null +++ b/include/configs/at91sam9g20ek.h @@ -0,0 +1,241 @@ +/* + * (C) Copyright 2008 + * ATMEL Corporation. + * + * Rick Bronson + * + * Configuation settings for the AT91SAM9260EK board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * If we are developing, we might want to start armboot from ram + * so we MUST NOT initialize critical regs like mem-timing ... + */ + +/* ARM asynchronous clock */ +#define AT91C_MASTER_CLOCK 132096000 /* peripheral clock */ + + +#define AT91_SLOW_CLOCK 32768 /* slow clock */ + +#define CFG_HZ 1000 + +#define CONFIG_AT91SAM9260EK 1 /* on an AT91SAM9260EK Board */ +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +/* define this to include the functionality of boot.bin in u-boot */ +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SKIP_RELOCATE_UBOOT +/* + * Size of malloc() pool + */ +#define CFG_MALLOC_LEN (3*CFG_ENV_SIZE + 128*1024) +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ + +#define CONFIG_BAUDRATE 115200 + +/* + * Hardware drivers + */ + +/* define one of these to choose the DBGU, USART0 or USART1 as console */ +#define CONFIG_DBGU 1 +#undef CONFIG_USART0 +#undef CONFIG_USART1 +#undef CONFIG_USART2 + +#undef CONFIG_HWFLOW /* don't include RTS/CTS flow control support */ + +#undef CONFIG_MODEM_SUPPORT /* disable modem initialization stuff */ + +#define CONFIG_BOOTDELAY 3 + +/* #define CONFIG_ENV_OVERWRITE 1 */ +#define BOARD_LATE_INIT 1 + +#define CONFIG_COMMANDS \ + ((CONFIG_CMD_DFL | \ + CFG_CMD_NET | \ + CFG_CMD_PING | \ + CFG_CMD_ENV | \ + CFG_CMD_USB | \ + CFG_CMD_FLASH | \ + CFG_CMD_NAND | \ + CFG_CMD_AUTOSCRIPT | \ + CFG_CMD_FAT ) & \ + ~(CFG_CMD_BDI | \ + CFG_CMD_IMLS | \ + CFG_CMD_IMI | \ + CFG_CMD_FPGA | \ + CFG_CMD_MISC | \ + CFG_CMD_LOADS)) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#define NAND_MAX_CHIPS 1 /* Max number of NAND devices */ +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define CFG_NAND_BASE 0x40000000 +#define CONFIG_NEW_NAND_CODE + +#define ADDR_COLUMN 1 +#define ADDR_PAGE 2 +#define ADDR_COLUMN_PAGE 3 + +#define NAND_ChipID_UNKNOWN 0 +#define NAND_MAX_FLOORS 1 +#undef CFG_NAND_WP + + + +/* These timings are specific to MT29F2G16AAB 256Mb (Micron) + * at MCK = 100 MHZ + */ + +#define AT91C_SM_NWE_SETUP (0 << 0) +#define AT91C_SM_NCS_WR_SETUP (0 << 8) +#define AT91C_SM_NRD_SETUP (0 << 16) +#define AT91C_SM_NCS_RD_SETUP (0 << 24) + +#define AT91C_SM_NWE_PULSE (4 << 0) +#define AT91C_SM_NCS_WR_PULSE (6 << 8) +#define AT91C_SM_NRD_PULSE (3 << 16) +#define AT91C_SM_NCS_RD_PULSE (5 << 24) + +#define AT91C_SM_NWE_CYCLE (6 << 0) +#define AT91C_SM_NRD_CYCLE (5 << 16) + +#define AT91C_SM_TDF (1 << 16) + + + +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM 0x20000000 +#define PHYS_SDRAM_SIZE 0x4000000 /* 64 megs */ + +#define CFG_MEMTEST_START PHYS_SDRAM +#define CFG_MEMTEST_END CFG_MEMTEST_START + PHYS_SDRAM_SIZE - 262144 + +#define CONFIG_DRIVER_ETHER 1 +#define CONFIG_AT91C_USE_RMII 1 +#define AT91C_PHY_ADDR 0 +#define AT91C_ETH_TIMEOUT 120000 +#define CONFIG_NET_RETRY_COUNT 5000 +#define CONFIG_TFTP_TIMEOUT 2500 + +#define CONFIG_HAS_DATAFLASH 1 +#define CFG_SPI_WRITE_TOUT (50*CFG_HZ) + +/* AC Characteristics */ +/* DLYBS = tCSS = 250ns min and DLYBCT = tCSH = 250ns */ +#define DATAFLASH_TCSS (0x22 << 16) +#define DATAFLASH_TCHS (0x1 << 24) + +#define CFG_MAX_DATAFLASH_BANKS 2 +#define CFG_MAX_DATAFLASH_PAGES 16384 +#define CFG_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* Logical adress for CS0 */ +#define CFG_DATAFLASH_LOGIC_ADDR_CS1 0xD0000000 /* Logical adress for CS1 */ + +#define CFG_NO_FLASH 1 +#define PHYS_FLASH_1 0x10000000 +#define PHYS_FLASH_SIZE 0x800000 /* 2 megs main flash */ +#define CFG_FLASH_BASE PHYS_FLASH_1 +#define CFG_MAX_FLASH_BANKS 1 +#define CFG_MAX_FLASH_SECT 256 +#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */ + +#undef CFG_ENV_IS_IN_FLASH +#define CFG_ENV_IS_IN_DATAFLASH 1 +#undef CFG_ENV_IS_IN_NAND + +#ifdef CFG_ENV_IS_IN_NAND +#define CFG_ENV_OFFSET 0x60000 /* environment starts here */ +#define CFG_ENV_OFFSET_REDUND 0x80000 /* redundant environment starts here */ +#define CFG_ENV_SIZE 0x20000 /* 1 sector = 128kB */ +#endif + +#ifdef CFG_ENV_IS_IN_DATAFLASH +#define CFG_ENV_OFFSET 0x4000 +#define CFG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS1 + CFG_ENV_OFFSET) +#define CFG_ENV_SIZE 0x4000 /* 0x8000 */ +#endif + +#ifdef CFG_ENV_IS_IN_FLASH +#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0xe000) /* between boot.bin and u-boot.bin.gz */ +#define CFG_ENV_SIZE 0x2000 /* 0x8000 */ +#endif + +/* Add USB stuff */ +#define CONFIG_USB_OHCI 1 +#define CONFIG_USB_STORAGE 1 +#define CONFIG_DOS_PARTITION 1 +#define LITTLEENDIAN 1 + +#define CFG_LOAD_ADDR 0x23f00000 /* default load address */ + +#define CFG_BOOT_SIZE 0x6000 /* 24 KBytes */ +#define CFG_U_BOOT_BASE (PHYS_FLASH_1 + 0x10000) +#define CFG_U_BOOT_SIZE 0x10000 /* 64 KBytes */ + + +#define CFG_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } +#define CFG_CONSOLE_IS_SERIAL +#undef CFG_CONSOLE_IS_LCD +#define CFG_PROMPT "U-Boot> " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ + + +#ifndef __ASSEMBLY__ +/*----------------------------------------------------------------------- + * Board specific extension for bd_info + * + * This structure is embedded in the global bd_info (bd_t) structure + * and can be used by the board specific code (eg board/...) + */ + +struct bd_info_ext { + /* helper variable for board environment handling + * + * env_crc_valid == 0 => uninitialised + * env_crc_valid > 0 => environment crc in flash is valid + * env_crc_valid < 0 => environment crc in flash is invalid + */ + int env_crc_valid; +}; +#endif + + +#define CONFIG_STACKSIZE (32*1024) /* regular stack */ + +#ifdef CONFIG_USE_IRQ +#error CONFIG_USE_IRQ not supported +#endif + +#endif -- cgit v1.2.3