summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorMateusz Majchrzycki <mmajchrzycki@namticro.com>2014-04-04 16:10:40 +0200
committerMateusz Majchrzycki <mmajchrzycki@namticro.com>2014-04-04 16:10:40 +0200
commitbe7c5a8d250793e1691bde8e2d93f3b2903dee04 (patch)
tree113689f45c9082c57218d80c408b52132b897f87
parent4df65c1035f9fbfa02f694b6e5ea6d2449eae2c0 (diff)
hal/io/misc: fix in registers definitions and hal_get_core_num
Fix in bits definitions in CYGHWR_HAL_VYBRID_MSCM_IRSPRCn (wrong bit numbering). Fix in hal_get_core_num (bad register io handling)
-rw-r--r--ecos/packages/hal/cortexm/vybrid/var/current/include/var_io.h4
-rw-r--r--ecos/packages/hal/cortexm/vybrid/var/current/src/vybrid_misc.c5
2 files changed, 6 insertions, 3 deletions
diff --git a/ecos/packages/hal/cortexm/vybrid/var/current/include/var_io.h b/ecos/packages/hal/cortexm/vybrid/var/current/include/var_io.h
index 4e01990..33824f7 100644
--- a/ecos/packages/hal/cortexm/vybrid/var/current/include/var_io.h
+++ b/ecos/packages/hal/cortexm/vybrid/var/current/include/var_io.h
@@ -129,9 +129,9 @@
#define CYGHWR_HAL_VYBRID_MSCM_IRCPGIR_TLF_S 24
#define CYGHWR_HAL_VYBRID_MSCM_IRSPRCn_BASE (CYGHWR_HAL_VYBRID_MSCM_BASE + 0x880)
#define CYGHWR_HAL_VYBRID_MSCM_IRSPRCn_CP1En_M 0x0002
-#define CYGHWR_HAL_VYBRID_MSCM_IRSPRCn_CP1En_S 0
+#define CYGHWR_HAL_VYBRID_MSCM_IRSPRCn_CP1En_S 1
#define CYGHWR_HAL_VYBRID_MSCM_IRSPRCn_CP0En_M 0x0001
-#define CYGHWR_HAL_VYBRID_MSCM_IRSPRCn_CP0En_S 1
+#define CYGHWR_HAL_VYBRID_MSCM_IRSPRCn_CP0En_S 0
#define CYGHWR_HAL_VYBRID_MSCM_IRSPRCn_RO_M 0x8000
#define CYGHWR_HAL_VYBRID_MSCM_IRSPRCn_RO_S 15
diff --git a/ecos/packages/hal/cortexm/vybrid/var/current/src/vybrid_misc.c b/ecos/packages/hal/cortexm/vybrid/var/current/src/vybrid_misc.c
index 751b8c0..aa0e4fa 100644
--- a/ecos/packages/hal/cortexm/vybrid/var/current/src/vybrid_misc.c
+++ b/ecos/packages/hal/cortexm/vybrid/var/current/src/vybrid_misc.c
@@ -231,7 +231,10 @@ hal_clock_disable(cyg_uint32 ccgr)
int
hal_get_core_num(void)
{
- return CYGHWR_HAL_VYBRID_MSCM_CPxNUM & CYGHWR_HAL_VYBRID_MSCM_CPxNUM_CPN_M;
+ cyg_uint32 reg;
+ HAL_READ_UINT32(CYGHWR_HAL_VYBRID_MSCM_CPxNUM, reg);
+
+ return (reg & CYGHWR_HAL_VYBRID_MSCM_CPxNUM_CPN_M);
}
//==========================================================================