diff options
| author | Mateusz Majchrzycki <mmajchrzycki@antmicro.com> | 2016-01-18 22:36:09 +0100 |
|---|---|---|
| committer | Mateusz Majchrzycki <mmajchrzycki@antmicro.com> | 2016-01-18 22:36:09 +0100 |
| commit | 852af2f553451dd8f2d69b3a473cef2d9c422d7f (patch) | |
| tree | 14f1c3724a3071c29bcf1eaa60c823df7a92a6fa | |
| parent | 480eb3fc824f349d5a2ec0a70afff7f826ad0d8a (diff) | |
imx7_colibri_m4: changed pinmux for I2C4, changed board I2C interface to I2C4
Pin assignment for I2C4 changed to redirect the bus to SODIMM pins 194 and 196 (standard Colibri I2C interface)
| -rw-r--r-- | examples/imx7_colibri_m4/board.h | 12 | ||||
| -rw-r--r-- | examples/imx7_colibri_m4/pin_mux.c | 34 |
2 files changed, 23 insertions, 23 deletions
diff --git a/examples/imx7_colibri_m4/board.h b/examples/imx7_colibri_m4/board.h index 7d531c1..e00c0a5 100644 --- a/examples/imx7_colibri_m4/board.h +++ b/examples/imx7_colibri_m4/board.h @@ -104,14 +104,14 @@ #define BOARD_MU_RDC_PDAP rdcPdapMuB /* I2C information for this board */ -#define BOARD_I2C_RDC_PDAP rdcPdapI2c2 -#define BOARD_I2C_CCM_ROOT ccmRootI2c2 -#define BOARD_I2C_CCM_CCGR ccmCcgrGateI2c2 -#define BOARD_I2C_BASEADDR I2C2 -#define BOARD_I2C_IRQ_NUM I2C2_IRQn -#define BOARD_I2C_HANDLER I2C2_Handler #define BOARD_I2C_FXAS21002_ADDR (0x20) #define BOARD_I2C_FXOS8700_ADDR (0x1E) +#define BOARD_I2C_RDC_PDAP rdcPdapI2c4 +#define BOARD_I2C_CCM_ROOT ccmRootI2c4 +#define BOARD_I2C_CCM_CCGR ccmCcgrGateI2c4 +#define BOARD_I2C_BASEADDR I2C4 +#define BOARD_I2C_IRQ_NUM I2C4_IRQn +#define BOARD_I2C_HANDLER I2C4_Handler /* FlexCAN information for this board */ #define BOARD_FLEXCAN_RDC_PDAP rdcPdapFlexCan2 diff --git a/examples/imx7_colibri_m4/pin_mux.c b/examples/imx7_colibri_m4/pin_mux.c index a6a382e..6c8cc0e 100644 --- a/examples/imx7_colibri_m4/pin_mux.c +++ b/examples/imx7_colibri_m4/pin_mux.c @@ -146,23 +146,23 @@ void configure_i2c_pins(I2C_Type* base) break; case I2C4_BASE: // I2C4 iomux configuration - IOMUXC_SW_MUX_CTL_PAD_SAI1_RX_SYNC = IOMUXC_SW_MUX_CTL_PAD_SAI1_RX_SYNC_MUX_MODE(3) | - IOMUXC_SW_MUX_CTL_PAD_SAI1_RX_SYNC_SION_MASK; - IOMUXC_SW_MUX_CTL_PAD_SAI1_RX_BCLK = IOMUXC_SW_MUX_CTL_PAD_SAI1_RX_BCLK_MUX_MODE(3) | - IOMUXC_SW_MUX_CTL_PAD_SAI1_RX_BCLK_SION_MASK; - - IOMUXC_I2C4_SCL_SELECT_INPUT = IOMUXC_I2C4_SCL_SELECT_INPUT_DAISY(3); - IOMUXC_I2C4_SDA_SELECT_INPUT = IOMUXC_I2C4_SDA_SELECT_INPUT_DAISY(3); - - IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_SYNC = IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_SYNC_PE_MASK | - IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_SYNC_PS(3) | - IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_SYNC_DSE(0) | - IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_SYNC_HYS_MASK; - - IOMUXC_SW_MUX_CTL_PAD_SAI1_RX_BCLK = IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_BCLK_PE_MASK | - IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_BCLK_PS(3) | - IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_BCLK_DSE(0) | - IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_BCLK_HYS_MASK; + IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD2 = IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD2_MUX_MODE(3) | // SCL + IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD2_SION_MASK; + IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD3 = IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD3_MUX_MODE(3) | // SDA + IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD3_SION_MASK; + + IOMUXC_I2C4_SCL_SELECT_INPUT = IOMUXC_I2C4_SCL_SELECT_INPUT_DAISY(4); + IOMUXC_I2C4_SDA_SELECT_INPUT = IOMUXC_I2C4_SDA_SELECT_INPUT_DAISY(4); + + IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD2 = IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD2_PE_MASK | + IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD2_PS(1) | + IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD2_DSE(0) | + IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD2_HYS_MASK; + + IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD3 = IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD3_PE_MASK | + IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD3_PS(1) | + IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD3_DSE(0) | + IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD3_HYS_MASK; break; default: break; |