diff options
| author | Zhang Bo <bo.zhang@nxp.com> | 2018-08-14 19:53:15 +0800 |
|---|---|---|
| committer | Zhang Bo <bo.zhang@nxp.com> | 2018-08-22 16:03:32 +0800 |
| commit | c9638440c0899fcd0ab714520f1b4b5e4ee2fbb1 (patch) | |
| tree | 838d83225a7f3b7f66a897d5b7c3ee2d0bcbee16 | |
| parent | 3f6f4d802aba3853eb6f7d96246213d6d8ba9db7 (diff) | |
imx8mq:plat: add noc priority configuration entry
Add NOC configuration entry for all the module.
Kernel can configure the noc priority through this entry.
Signed-off-by: Zhang Bo <bo.zhang@nxp.com>
| -rw-r--r-- | plat/imx/common/include/fsl_sip.h | 6 | ||||
| -rw-r--r-- | plat/imx/imx8mq/src.c | 28 |
2 files changed, 29 insertions, 5 deletions
diff --git a/plat/imx/common/include/fsl_sip.h b/plat/imx/common/include/fsl_sip.h index 219163d5..7246f8f7 100644 --- a/plat/imx/common/include/fsl_sip.h +++ b/plat/imx/common/include/fsl_sip.h @@ -49,6 +49,12 @@ #define FSL_SIP_NOC 0xc2000008 #define FSL_SIP_NOC_LCDIF 0x0 +#define FSL_SIP_NOC_PRIORITY 0x1 +#define NOC_GPU_PRIORITY 0x10 +#define NOC_DCSS_PRIORITY 0x11 +#define NOC_VPU_PRIORITY 0x12 +#define NOC_CPU_PRIORITY 0x13 +#define NOC_MIX_PRIORITY 0x14 #define FSL_SIP_WAKEUP_SRC 0xc2000009 #define FSL_SIP_WAKEUP_SRC_SCU 0x1 diff --git a/plat/imx/imx8mq/src.c b/plat/imx/imx8mq/src.c index abaf0547..eb36c239 100644 --- a/plat/imx/imx8mq/src.c +++ b/plat/imx/imx8mq/src.c @@ -71,8 +71,7 @@ int imx_soc_handler(uint32_t smc_fid, u_register_t x1, u_register_t x2, int imx_noc_handler(uint32_t smc_fid, u_register_t x1, u_register_t x2, u_register_t x3) { - switch(x1) { - case FSL_SIP_NOC_LCDIF: + if (FSL_SIP_NOC_LCDIF == x1) { /* config NOC for VPU */ mmio_write_32(IMX_NOC_BASE + 0x108, 0x34); mmio_write_32(IMX_NOC_BASE + 0x10c, 0x1); @@ -83,10 +82,29 @@ int imx_noc_handler(uint32_t smc_fid, u_register_t x1, u_register_t x2, mmio_write_32(IMX_NOC_BASE + 0x18c, 0x1); mmio_write_32(IMX_NOC_BASE + 0x190, 0x500); mmio_write_32(IMX_NOC_BASE + 0x194, 0x30); - break; - default: + } else if (FSL_SIP_NOC_PRIORITY == x1) { + switch(x2) { + case NOC_GPU_PRIORITY: + mmio_write_32(IMX_NOC_BASE + 0x008, x3); + break; + case NOC_DCSS_PRIORITY: + mmio_write_32(IMX_NOC_BASE + 0x088, x3); + break; + case NOC_VPU_PRIORITY: + mmio_write_32(IMX_NOC_BASE + 0x108, x3); + break; + case NOC_CPU_PRIORITY: + mmio_write_32(IMX_NOC_BASE + 0x188, x3); + break; + case NOC_MIX_PRIORITY: + mmio_write_32(IMX_NOC_BASE + 0x288, x3); + break; + default: + return SMC_UNK; + }; + } else { return SMC_UNK; - }; + } return 0; } |