diff options
| author | Bai Ping <ping.bai@nxp.com> | 2017-08-02 16:25:21 +0800 |
|---|---|---|
| committer | Bai Ping <ping.bai@nxp.com> | 2017-08-02 16:57:58 +0800 |
| commit | b106b018e4e2cf92006a2a51f444d4336eb0f9b0 (patch) | |
| tree | 3eaf6b9d2544ce6c210245bb4d43ca32c2014a74 | |
| parent | 4bc0aa353b8e0468d8e088e9d78cff2401803aa3 (diff) | |
imx8mq: fix the pcie power domain dependency
the PCIE1 and PCIE2 share the same reset signal, if PCIE2 is power down,
PCIE1 will also be power down, so when we need to power up PCIE1, the PCIE2
need to power up too, only PCIE1 is power down, the PCIE2 power domain can
be power down too
Signed-off-by: Bai Ping <ping.bai@nxp.com>
| -rw-r--r-- | plat/freescale/imx8mq/gpc.c | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/plat/freescale/imx8mq/gpc.c b/plat/freescale/imx8mq/gpc.c index d0b3a053..66323487 100644 --- a/plat/freescale/imx8mq/gpc.c +++ b/plat/freescale/imx8mq/gpc.c @@ -115,6 +115,7 @@ static uint32_t gpc_saved_imrs[128]; static uint32_t gpc_wake_irqs[128]; +static bool is_pcie1_power_down = true; static uint32_t gpc_pu_m_core_offset[11] = { 0xc00, 0xc40, 0xc80, 0xcc0, @@ -442,6 +443,24 @@ static void imx_gpc_pm_domain_enable(uint32_t domain_id, uint32_t on) uint32_t val; uintptr_t reg; + /* + * PCIE1 and PCIE2 share the same reset signal, if we power down + * PCIE2, PCIE1 will be hold in reset too. + * 1. when we want to power up PCIE1, the PCIE2 power domain also + * need to be power on; + * 2. when we want to power down PCIE2 power domain, we should make + * sure PCIE1 is already power down. + */ + if (domain_id == 1 && !on) { + is_pcie1_power_down = true; + } else if (domain_id == 1 && on) { + imx_gpc_pm_domain_enable(10, true); + is_pcie1_power_down = false; + } + + if (domain_id == 10 && !on && !is_pcie1_power_down) + return; + imx_gpc_set_m_core_pgc(gpc_pu_m_core_offset[domain_id], true); reg = IMX_GPC_BASE + (on ? 0xf8 : 0x104); |