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| author | Anson Huang <Anson.Huang@nxp.com> | 2017-07-19 21:54:38 +0800 |
|---|---|---|
| committer | Anson Huang <Anson.Huang@nxp.com> | 2017-07-19 21:54:38 +0800 |
| commit | bda85378508fd73ff6e9aa709de8c9ab1bad0dd0 (patch) | |
| tree | 3cc347aa87726c66e274818bf6611d50638d85ef | |
| parent | d22574b90dbbacbec87abf32bcc24a5274215f3a (diff) | |
imx8mq: gpc: power domain id needs to be mapped to register bit offset
The power domain id does NOT equal to the register bit
offset, so need to do a mapping here.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
| -rw-r--r-- | plat/freescale/imx8mq/gpc.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/plat/freescale/imx8mq/gpc.c b/plat/freescale/imx8mq/gpc.c index 9f795c7d..7938200a 100644 --- a/plat/freescale/imx8mq/gpc.c +++ b/plat/freescale/imx8mq/gpc.c @@ -445,7 +445,7 @@ static void imx_gpc_pm_domain_enable(uint32_t domain_id, uint32_t on) imx_gpc_set_m_core_pgc(gpc_pu_m_core_offset[domain_id], true); reg = IMX_GPC_BASE + (on ? 0xf8 : 0x104); - val = 1 << domain_id; + val = 1 << (domain_id > 3 ? (domain_id + 3) : domain_id); mmio_write_32(reg, val); while(mmio_read_32(reg) & val) ; |