diff options
| author | Anson Huang <Anson.Huang@nxp.com> | 2020-04-03 17:04:41 +0800 |
|---|---|---|
| committer | Anson Huang <Anson.Huang@nxp.com> | 2020-04-03 18:00:11 +0800 |
| commit | ffa4343ec424f1eacf86b4412e8ff5a6c01dc37b (patch) | |
| tree | 85113e24df1cf0b5f15d32a74390cdc9a4183c22 | |
| parent | d2ca874e7861d7987f7e831d32889a2ad334a53c (diff) | |
MLK-23742 plat: imx: No need to set cpu entry for reboot on i.MX8 with SCU
The SCFW supports OCRAM retention, so no need to set cpu entry for reboot
to let CPU run from SPL in OCRAM again when reboot, then SPL will reload
images after reboot.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
| -rw-r--r-- | plat/imx/imx8dxl/imx8dxl_psci.c | 6 | ||||
| -rw-r--r-- | plat/imx/imx8qm/imx8qm_psci.c | 10 | ||||
| -rw-r--r-- | plat/imx/imx8qx/imx8qx_psci.c | 6 |
3 files changed, 0 insertions, 22 deletions
diff --git a/plat/imx/imx8dxl/imx8dxl_psci.c b/plat/imx/imx8dxl/imx8dxl_psci.c index f8ffaf28..6e6a6ad6 100644 --- a/plat/imx/imx8dxl/imx8dxl_psci.c +++ b/plat/imx/imx8dxl/imx8dxl_psci.c @@ -244,11 +244,5 @@ int plat_setup_psci_ops(uintptr_t sec_entrypoint, sc_pm_req_sys_if_power_mode(ipc_handle, SC_R_A35, SC_PM_SYS_IF_INTERCONNECT, SC_PM_PW_MODE_ON, SC_PM_PW_MODE_ON); - /* - * set partition reboot address for primary CPU, boot device is NOT owned - * by ATF, so pass 0 here - */ - sc_pm_set_boot_parm(ipc_handle, SC_R_A35_0, BL31_BASE, SC_R_MU_0A, 0); - return 0; } diff --git a/plat/imx/imx8qm/imx8qm_psci.c b/plat/imx/imx8qm/imx8qm_psci.c index 7911bc9e..65cad5b0 100644 --- a/plat/imx/imx8qm/imx8qm_psci.c +++ b/plat/imx/imx8qm/imx8qm_psci.c @@ -303,9 +303,6 @@ static const plat_psci_ops_t imx_plat_psci_ops = { int plat_setup_psci_ops(uintptr_t sec_entrypoint, const plat_psci_ops_t **psci_ops) { - u_register_t mpidr = read_mpidr_el1(); - unsigned int cluster_id = MPIDR_AFFLVL1_VAL(mpidr); - imx_mailbox_init(sec_entrypoint); *psci_ops = &imx_plat_psci_ops; @@ -327,12 +324,5 @@ int plat_setup_psci_ops(uintptr_t sec_entrypoint, sc_pm_req_sys_if_power_mode(ipc_handle, SC_R_A72, SC_PM_SYS_IF_INTERCONNECT, SC_PM_PW_MODE_ON, SC_PM_PW_MODE_ON); - /* - * set partition reboot address for primary CPU, boot device is NOT owned - * by ATF, so pass 0 here - */ - sc_pm_set_boot_parm(ipc_handle, cluster_id == 0 ? SC_R_A53_0 : SC_R_A72_0, - BL31_BASE, SC_R_MU_0A, 0); - return 0; } diff --git a/plat/imx/imx8qx/imx8qx_psci.c b/plat/imx/imx8qx/imx8qx_psci.c index 2d8ca5c3..24a46f7a 100644 --- a/plat/imx/imx8qx/imx8qx_psci.c +++ b/plat/imx/imx8qx/imx8qx_psci.c @@ -244,11 +244,5 @@ int plat_setup_psci_ops(uintptr_t sec_entrypoint, sc_pm_req_sys_if_power_mode(ipc_handle, SC_R_A35, SC_PM_SYS_IF_INTERCONNECT, SC_PM_PW_MODE_ON, SC_PM_PW_MODE_ON); - /* - * set partition reboot address for primary CPU, boot device is NOT owned - * by ATF, so pass 0 here - */ - sc_pm_set_boot_parm(ipc_handle, SC_R_A35_0, BL31_BASE, SC_R_MU_0A, 0); - return 0; } |