diff options
author | Jacky Bai <ping.bai@nxp.com> | 2020-04-17 15:01:18 +0800 |
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committer | Jacky Bai <ping.bai@nxp.com> | 2020-04-23 20:26:45 +0800 |
commit | 0d6f7ad150169ffc2b238e4f76c03d9fbfc468e3 (patch) | |
tree | 877bdcda144193826461f2eccbf64e4da6e1872b | |
parent | ee6e0f2781f2ab43b3eb5b66f7a6100f1a3a8450 (diff) |
MLK-23805-01 plat: imx8mp: Correct the MU IRQ mask reg offset
Correct the GPC IMR register offset of MU IRQ mask.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
-rw-r--r-- | plat/imx/imx8m/imx8mp/gpc.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/plat/imx/imx8m/imx8mp/gpc.c b/plat/imx/imx8m/imx8mp/gpc.c index 4556b80c..471311e3 100644 --- a/plat/imx/imx8m/imx8mp/gpc.c +++ b/plat/imx/imx8m/imx8mp/gpc.c @@ -188,7 +188,7 @@ void imx_set_sys_wakeup(unsigned int last_core, bool pdn) /* enable the MU wakeup */ if (imx_m4_lpa_active()) - mmio_clrbits_32(IMX_GPC_BASE + gpc_imr_offset[last_core] + 0x8, BIT(24)); + mmio_clrbits_32(gpc_imr_offset[last_core] + 0x8, BIT(24)); } static void imx_gpc_hwirq_mask(unsigned int hwirq) |