diff options
author | Jacky Bai <ping.bai@nxp.com> | 2020-01-10 17:46:31 +0800 |
---|---|---|
committer | Jacky Bai <ping.bai@nxp.com> | 2020-02-09 20:58:49 +0800 |
commit | 1440ea94c250893829b16ccc30a19cdde5dc5636 (patch) | |
tree | a2e9a6ff70e3c537d33477b150b07b41837da411 | |
parent | e2e707222beeb14986d5853b135ed767f0e112ff (diff) |
plat: imx8mq: Correct the slot ack setting for STOP mode
A53 core's power up ack need to be used when system resume
from DSM mode.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
-rw-r--r-- | plat/imx/imx8m/imx8mq/gpc.c | 2 | ||||
-rw-r--r-- | plat/imx/imx8m/imx8mq/imx8mq_psci.c | 2 | ||||
-rw-r--r-- | plat/imx/imx8m/include/gpc.h | 1 |
3 files changed, 3 insertions, 2 deletions
diff --git a/plat/imx/imx8m/imx8mq/gpc.c b/plat/imx/imx8m/imx8mq/gpc.c index 2baa027e..6c0a057b 100644 --- a/plat/imx/imx8m/imx8mq/gpc.c +++ b/plat/imx/imx8m/imx8mq/gpc.c @@ -233,7 +233,7 @@ void imx_pup_pdn_slot_config(int last_core, bool pdn) mmio_setbits_32(IMX_GPC_BASE + SLTx_CFG(2), SLT_COREx_PUP(last_core)); /* ACK setting: PLAT ACK for PDN, CORE ACK for PUP */ mmio_clrsetbits_32(IMX_GPC_BASE + PGC_ACK_SEL_A53, 0xFFFFFFFF, - A53_PLAT_PDN_ACK | A53_PLAT_PUP_ACK); + A53_PLAT_PDN_ACK | SLT_COREx_PUP_ACK(last_core)); } else { mmio_clrbits_32(IMX_GPC_BASE + SLTx_CFG(0), 0xFFFFFFFF); mmio_clrbits_32(IMX_GPC_BASE + SLTx_CFG(1), 0xFFFFFFFF); diff --git a/plat/imx/imx8m/imx8mq/imx8mq_psci.c b/plat/imx/imx8m/imx8mq/imx8mq_psci.c index a2ed2077..3415c4ed 100644 --- a/plat/imx/imx8m/imx8mq/imx8mq_psci.c +++ b/plat/imx/imx8m/imx8mq/imx8mq_psci.c @@ -90,8 +90,8 @@ void imx_domain_suspend_finish(const psci_power_state_t *target_state) /* check the system level status */ if (is_local_state_retn(SYSTEM_PWR_STATE(target_state))) { - dram_exit_retention(); imx_anamix_override(true); + dram_exit_retention(); imx_set_sys_lpm(core_id, false); imx_clear_rbc_count(); } diff --git a/plat/imx/imx8m/include/gpc.h b/plat/imx/imx8m/include/gpc.h index 016e55d1..8ae19d28 100644 --- a/plat/imx/imx8m/include/gpc.h +++ b/plat/imx/imx8m/include/gpc.h @@ -86,6 +86,7 @@ #define COREx_LPM_PUP(core_id) ((core_id) < 2 ? (1 << ((core_id) * 2 + 9)) : (1 << ((core_id) * 2 + 21))) #define SLTx_CFG(n) ((SLT0_CFG + ((n) * 4))) #define SLT_COREx_PUP(core_id) (0x2 << ((core_id) * 2)) +#define SLT_COREx_PUP_ACK(core_id) ((core_id) < 2 ? (1 << ((core_id) + 16)) : (1 << ((core_id) + 27))) #define IRQ_IMR_NUM 4 #define IMR_MASK_ALL 0xffffffff |