diff options
| author | Jacky Bai <ping.bai@nxp.com> | 2020-03-27 20:28:19 +0800 |
|---|---|---|
| committer | Jacky Bai <ping.bai@nxp.com> | 2020-03-27 20:52:50 +0800 |
| commit | bd5f9fbc6b1fc9dd1f15c72e9a92195825c0f1ba (patch) | |
| tree | 30bf0a74eb4dbb4478cc26d79a716d6f2f881256 | |
| parent | 6fb60390abd1329e360953b835e82c9a50c042fc (diff) | |
plat: imx8mp: Enable BL32 fdt overlay support on imx8mp
Allow OP-TEE to generate a device-tree overlay binary
that will be applied by u-boot on the regular dtb.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
| -rw-r--r-- | plat/imx/imx8m/imx8mp/imx8mp_bl31_setup.c | 13 | ||||
| -rw-r--r-- | plat/imx/imx8m/imx8mp/include/platform_def.h | 2 |
2 files changed, 11 insertions, 4 deletions
diff --git a/plat/imx/imx8m/imx8mp/imx8mp_bl31_setup.c b/plat/imx/imx8m/imx8mp/imx8mp_bl31_setup.c index d5c4a38e..d26d342d 100644 --- a/plat/imx/imx8m/imx8mp/imx8mp_bl31_setup.c +++ b/plat/imx/imx8m/imx8mp/imx8mp_bl31_setup.c @@ -165,14 +165,19 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, bl32_image_ep_info.pc = BL32_BASE; bl32_image_ep_info.spsr = 0; + /* Pass TEE base and size to bl33 */ + bl33_image_ep_info.args.arg1 = BL32_BASE; + bl33_image_ep_info.args.arg2 = BL32_SIZE; + #ifdef SPD_trusty bl32_image_ep_info.args.arg0 = BL32_SIZE; bl32_image_ep_info.args.arg1 = BL32_BASE; +#else + /* Make sure memory is clean */ + mmio_write_32(BL32_FDT_OVERLAY_ADDR, 0); + bl33_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR; + bl32_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR; #endif - - /* Pass TEE base and size to bl33 */ - bl33_image_ep_info.args.arg1 = BL32_BASE; - bl33_image_ep_info.args.arg2 = BL32_SIZE; #endif bl31_tzc380_setup(); diff --git a/plat/imx/imx8m/imx8mp/include/platform_def.h b/plat/imx/imx8m/imx8mp/include/platform_def.h index 088201fa..bcd45343 100644 --- a/plat/imx/imx8m/imx8mp/include/platform_def.h +++ b/plat/imx/imx8m/imx8mp/include/platform_def.h @@ -37,6 +37,8 @@ /* non-secure uboot base */ #define PLAT_NS_IMAGE_OFFSET U(0x40200000) +#define BL32_FDT_OVERLAY_ADDR (PLAT_NS_IMAGE_OFFSET + 0x3000000) + /* GICv3 base address */ #define PLAT_GICD_BASE U(0x38800000) #define PLAT_GICR_BASE U(0x38880000) |