diff options
| author | Jacky Bai <ping.bai@nxp.com> | 2020-10-22 14:35:12 +0800 |
|---|---|---|
| committer | Jacky Bai <ping.bai@nxp.com> | 2020-10-28 09:38:47 +0800 |
| commit | a9ecd1f1ff6d213e4f13a35aa07a69445b6a1b55 (patch) | |
| tree | a2497016d0a1d0644cd61a1d6eaf6cd071424602 | |
| parent | 48733cb4e773a7584ced601de9d717efa3d73815 (diff) | |
MLK-24920 plat: imx8m: Fix the dram retention random hang on some imx8mq Rev2.0
It seems the DRAM APB clock root slice can NOT work normally
if the PLLs is power down in DSM mode. So update this clock
slice's setting explictly to make it work. This piece of code
is there for a long while on previous release, so just add
it back to align with previous flow.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
| -rw-r--r-- | plat/imx/imx8m/ddr/dram_retention.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/plat/imx/imx8m/ddr/dram_retention.c b/plat/imx/imx8m/ddr/dram_retention.c index 2dd79b61..685526f4 100644 --- a/plat/imx/imx8m/ddr/dram_retention.c +++ b/plat/imx/imx8m/ddr/dram_retention.c @@ -126,6 +126,10 @@ void dram_exit_retention(void) mmio_write_32(CCM_CCGR(5), 2); mmio_write_32(CCM_SRC_CTRL(15), 2); + /* change the clock source of dram_apb_clk_root */ + mmio_write_32(0x3038a088, (0x7 << 24) | (0x7 << 16)); + mmio_write_32(0x3038a084, (0x4 << 24) | (0x3 << 16)); + /* disable iso */ mmio_setbits_32(IMX_GPC_BASE + PU_PGC_UP_TRG, DDRMIX_PWR_REQ); mmio_write_32(SRC_DDR1_RCR, 0x8F000006); |