diff options
| author | Jacky Bai <ping.bai@nxp.com> | 2020-04-07 15:08:03 +0800 |
|---|---|---|
| committer | Jacky Bai <ping.bai@nxp.com> | 2020-04-07 17:08:59 +0800 |
| commit | cece288ccd11dec1f6b9317af75761d8d2fbce8d (patch) | |
| tree | 356bb3caaa8560c7198ffe48ad2522bb996d5279 | |
| parent | bfbf223ed855d31085d0a6469aa94357ae0c3674 (diff) | |
MLK-23752 plat: imx8m: Update the src gpr used for imx8mp lpa
On i.MX8MP, the SRC GPR9(0x94) is used by memory repair, so choose
SRC GPR10(0x98) as the LPA status sync register. Add use '==' instead
of '&' for LPA active statue check.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
| -rw-r--r-- | plat/imx/imx8m/gpc_common.c | 3 | ||||
| -rw-r--r-- | plat/imx/imx8m/imx8mm/include/platform_def.h | 1 | ||||
| -rw-r--r-- | plat/imx/imx8m/imx8mn/include/platform_def.h | 1 | ||||
| -rw-r--r-- | plat/imx/imx8m/imx8mp/include/platform_def.h | 1 |
4 files changed, 4 insertions, 2 deletions
diff --git a/plat/imx/imx8m/gpc_common.c b/plat/imx/imx8m/gpc_common.c index 5c996e20..400341ce 100644 --- a/plat/imx/imx8m/gpc_common.c +++ b/plat/imx/imx8m/gpc_common.c @@ -24,7 +24,6 @@ #define M4_LPA_ACTIVE 0x5555 #define M4_LPA_IDLE 0x0 -#define LPA_STATUS U(0x94) static uint32_t gpc_imr_offset[] = { IMR1_CORE0_A53, IMR1_CORE1_A53, @@ -42,7 +41,7 @@ struct plat_gic_ctx imx_gicv3_ctx; bool imx_m4_lpa_active(void) { - return mmio_read_32(IMX_SRC_BASE + LPA_STATUS) & M4_LPA_ACTIVE; + return mmio_read_32(IMX_SRC_BASE + LPA_STATUS) == M4_LPA_ACTIVE; } bool imx_is_m4_enabled(void) diff --git a/plat/imx/imx8m/imx8mm/include/platform_def.h b/plat/imx/imx8m/imx8mm/include/platform_def.h index 61ccbed0..42b03613 100644 --- a/plat/imx/imx8m/imx8mm/include/platform_def.h +++ b/plat/imx/imx8m/imx8mm/include/platform_def.h @@ -122,6 +122,7 @@ #define SRC_SCR_M4C_NON_SCLR_RST_MASK BIT(0) #define IMX_M4_STATUS (IMX_SRC_BASE + SRC_M4RCR) #define IMX_M4_ENABLED_MASK SRC_SCR_M4C_NON_SCLR_RST_MASK +#define LPA_STATUS U(0x94) #define SNVS_LPCR U(0x38) #define SNVS_LPCR_SRTC_ENV BIT(0) diff --git a/plat/imx/imx8m/imx8mn/include/platform_def.h b/plat/imx/imx8m/imx8mn/include/platform_def.h index 2e3e0b69..967afbbe 100644 --- a/plat/imx/imx8m/imx8mn/include/platform_def.h +++ b/plat/imx/imx8m/imx8mn/include/platform_def.h @@ -128,6 +128,7 @@ #define GPR_CM7_CPUWAIT BIT(0) #define IMX_M4_STATUS (IMX_IOMUX_GPR_BASE + IOMUXC_GPR22) #define IMX_M4_ENABLED_MASK GPR_CM7_CPUWAIT +#define LPA_STATUS U(0x94) #define ANAMIX_MISC_CTL U(0x124) diff --git a/plat/imx/imx8m/imx8mp/include/platform_def.h b/plat/imx/imx8m/imx8mp/include/platform_def.h index ecbe0c5f..ce279a56 100644 --- a/plat/imx/imx8m/imx8mp/include/platform_def.h +++ b/plat/imx/imx8m/imx8mp/include/platform_def.h @@ -130,6 +130,7 @@ #define GPR_CM7_CPUWAIT BIT(0) #define IMX_M4_STATUS (IMX_IOMUX_GPR_BASE + IOMUXC_GPR22) #define IMX_M4_ENABLED_MASK GPR_CM7_CPUWAIT +#define LPA_STATUS U(0x98) #define ANAMIX_MISC_CTL U(0x124) |