diff options
| author | Jacky Bai <ping.bai@nxp.com> | 2020-09-25 10:25:15 +0800 |
|---|---|---|
| committer | Jacky Bai <ping.bai@nxp.com> | 2020-10-23 18:04:53 +0800 |
| commit | d7d1788db782a7c960bddbf9d4cb442b0488d37b (patch) | |
| tree | 3c533b21b68296c0c45943794cb00d566b2f726d | |
| parent | 5d80923c8c440ebf4449adf44c05932c35a24a9b (diff) | |
MLK-24914-01 plat: imx8mp: Remove vpu reset & memrepair workaround
The VPU reset & memrepair workaround is only for i.MX8MP
A0 silicon. As the A0 will not be supported anymore, so
drop these workaround
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Jian Li <jian.li@nxp.com>
| -rw-r--r-- | plat/imx/imx8m/imx8mp/gpc.c | 23 |
1 files changed, 0 insertions, 23 deletions
diff --git a/plat/imx/imx8m/imx8mp/gpc.c b/plat/imx/imx8m/imx8mp/gpc.c index ed1f6c11..7d004e25 100644 --- a/plat/imx/imx8m/imx8mp/gpc.c +++ b/plat/imx/imx8m/imx8mp/gpc.c @@ -391,9 +391,6 @@ void imx_gpc_pm_domain_enable(uint32_t domain_id, bool on) if (domain_id == VPU_H1) mmio_clrbits_32(IMX_VPU_BLK_BASE + 0x4, BIT(2)); - /* disable the memory repair clock before power up */ - mmio_write_32(IMX_CCM_BASE + 0x4640, 0x0); - /* clear the PGC bit */ mmio_clrbits_32(IMX_GPC_BASE + pwr_domain->pgc_offset, 0x1); @@ -403,9 +400,6 @@ void imx_gpc_pm_domain_enable(uint32_t domain_id, bool on) /* wait for power request done */ while (mmio_read_32(IMX_GPC_BASE + PU_PGC_UP_TRG) & pwr_domain->pwr_req); - /* enable the memory repair clock after power up */ - mmio_write_32(IMX_CCM_BASE + 0x4640, 0x3); - /* wait for memory repair done */ wait_memrepair_done(domain_id); @@ -466,29 +460,12 @@ void imx_gpc_pm_domain_enable(uint32_t domain_id, bool on) /* set the PGC bit */ mmio_setbits_32(IMX_GPC_BASE + pwr_domain->pgc_offset, 0x1); - /* - * leave the G1, G2, H1 power domain on until VPUMIX power off, - * otherwise system will hang due to VPUMIX ACK - */ - if (domain_id == VPU_H1 || domain_id == VPU_G1 || domain_id == VPU_G2) - return; - - /* disable the memory repair clock before power down */ - mmio_write_32(IMX_CCM_BASE + 0x4640, 0x0); - - if (domain_id == VPUMIX) - mmio_write_32(IMX_GPC_BASE + PU_PGC_DN_TRG, VPU_G1_PWR_REQ | - VPU_G2_PWR_REQ | VPU_H1_PWR_REQ); - /* power down the domain */ mmio_setbits_32(IMX_GPC_BASE + PU_PGC_DN_TRG, pwr_domain->pwr_req); /* wait for power request done */ while (mmio_read_32(IMX_GPC_BASE + PU_PGC_DN_TRG) & pwr_domain->pwr_req); - /* enable the memory repair clock after power down */ - mmio_write_32(IMX_CCM_BASE + 0x4640, 0x3); - if (domain_id == HDMIMIX) { /* disable all the clocks of HDMIMIX */ mmio_write_32(0x32fc0040, 0x0); |