diff options
| author | Andrew Thoelke <andrew.thoelke@arm.com> | 2014-04-28 12:28:39 +0100 |
|---|---|---|
| committer | Andrew Thoelke <andrew.thoelke@arm.com> | 2014-05-07 11:19:47 +0100 |
| commit | 8cec598ba3b689b86d9dfc58bca5610bdc48f55a (patch) | |
| tree | 10a3622d6a57fe02b45112fd512297238ad93dc5 /bl1/aarch64 | |
| parent | e404d7f44a190b82332bb96daffa0c6239732218 (diff) | |
Correct usage of data and instruction barriers
The current code does not always use data and instruction
barriers as required by the architecture and frequently uses
barriers excessively due to their inclusion in all of the
write_*() helper functions.
Barriers should be used explicitly in assembler or C code
when modifying processor state that requires the barriers in
order to enable review of correctness of the code.
This patch removes the barriers from the helper functions and
introduces them as necessary elsewhere in the code.
PORTING NOTE: check any port of Trusted Firmware for use of
system register helper functions for reliance on the previous
barrier behaviour and add explicit barriers as necessary.
Fixes ARM-software/tf-issues#92
Change-Id: Ie63e187404ff10e0bdcb39292dd9066cb84c53bf
Diffstat (limited to 'bl1/aarch64')
| -rw-r--r-- | bl1/aarch64/bl1_arch_setup.c | 1 | ||||
| -rw-r--r-- | bl1/aarch64/bl1_entrypoint.S | 1 | ||||
| -rw-r--r-- | bl1/aarch64/bl1_exceptions.S | 1 |
3 files changed, 2 insertions, 1 deletions
diff --git a/bl1/aarch64/bl1_arch_setup.c b/bl1/aarch64/bl1_arch_setup.c index 758b8e8f..a1ebbdb2 100644 --- a/bl1/aarch64/bl1_arch_setup.c +++ b/bl1/aarch64/bl1_arch_setup.c @@ -44,6 +44,7 @@ void bl1_arch_setup(void) tmp_reg |= (SCTLR_A_BIT | SCTLR_SA_BIT); tmp_reg &= ~SCTLR_EE_BIT; write_sctlr_el3(tmp_reg); + isb(); /* * Enable HVCs, route FIQs to EL3, set the next EL to be AArch64, route diff --git a/bl1/aarch64/bl1_entrypoint.S b/bl1/aarch64/bl1_entrypoint.S index 012b779c..e25386f7 100644 --- a/bl1/aarch64/bl1_entrypoint.S +++ b/bl1/aarch64/bl1_entrypoint.S @@ -86,7 +86,6 @@ func bl1_entrypoint mrs x0, sctlr_el3 orr x0, x0, #SCTLR_I_BIT msr sctlr_el3, x0 - isb _wait_for_entrypoint: diff --git a/bl1/aarch64/bl1_exceptions.S b/bl1/aarch64/bl1_exceptions.S index 68d088b7..7f930d83 100644 --- a/bl1/aarch64/bl1_exceptions.S +++ b/bl1/aarch64/bl1_exceptions.S @@ -221,6 +221,7 @@ func process_exception bl read_sctlr_el3 bic x0, x0, x1 bl write_sctlr_el3 + isb mov x0, #DCCISW bl dcsw_op_all bl tlbialle3 |