diff options
| author | Dan Handley <dan.handley@arm.com> | 2014-08-19 11:04:21 +0100 |
|---|---|---|
| committer | Dan Handley <dan.handley@arm.com> | 2014-08-19 11:04:21 +0100 |
| commit | a1d80440c44ce70e5fec4d8c60b5f6688b6cf8ff (patch) | |
| tree | 27877c106f03eed314f529ee05e66cb747e1914b /bl1 | |
| parent | 57a18ff489fcfba38f26845eafacd90479c0be81 (diff) | |
| parent | 0c8d4fef28768233f1f46b4d085f904293dffd2c (diff) | |
Merge pull request #189 from achingupta/ag/tf-issues#153
Unmask SError interrupt and clear SCR_EL3.EA bit
Diffstat (limited to 'bl1')
| -rw-r--r-- | bl1/aarch64/bl1_arch_setup.c | 13 | ||||
| -rw-r--r-- | bl1/aarch64/bl1_entrypoint.S | 8 | ||||
| -rw-r--r-- | bl1/aarch64/bl1_exceptions.S | 3 |
3 files changed, 13 insertions, 11 deletions
diff --git a/bl1/aarch64/bl1_arch_setup.c b/bl1/aarch64/bl1_arch_setup.c index eeaa24af..6a3f0623 100644 --- a/bl1/aarch64/bl1_arch_setup.c +++ b/bl1/aarch64/bl1_arch_setup.c @@ -37,17 +37,8 @@ ******************************************************************************/ void bl1_arch_setup(void) { - /* - * Set the next EL to be AArch64, route external abort and SError - * interrupts to EL3 - */ - write_scr_el3(SCR_RES1_BITS | SCR_RW_BIT | SCR_EA_BIT); - - /* - * Enable SError and Debug exceptions - */ - enable_serror(); - enable_debug_exceptions(); + /* Set the next EL to be AArch64 */ + write_scr_el3(SCR_RES1_BITS | SCR_RW_BIT); } /******************************************************************************* diff --git a/bl1/aarch64/bl1_entrypoint.S b/bl1/aarch64/bl1_entrypoint.S index dd7d78fe..e7f92c71 100644 --- a/bl1/aarch64/bl1_entrypoint.S +++ b/bl1/aarch64/bl1_entrypoint.S @@ -76,6 +76,14 @@ func bl1_entrypoint */ adr x0, bl1_exceptions msr vbar_el3, x0 + isb + + /* --------------------------------------------- + * Enable the SError interrupt now that the + * exception vectors have been setup. + * --------------------------------------------- + */ + msr daifclr, #DAIF_ABT_BIT /* --------------------------------------------------------------------- * The initial state of the Architectural feature trap register diff --git a/bl1/aarch64/bl1_exceptions.S b/bl1/aarch64/bl1_exceptions.S index 8ab9df86..13b34b79 100644 --- a/bl1/aarch64/bl1_exceptions.S +++ b/bl1/aarch64/bl1_exceptions.S @@ -112,6 +112,9 @@ SErrorSPx: */ .align 7 SynchronousExceptionA64: + /* Enable the SError interrupt */ + msr daifclr, #DAIF_ABT_BIT + /* ------------------------------------------------ * Only a single SMC exception from BL2 to ask * BL1 to pass EL3 control to BL31 is expected |