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author | Jeenu Viswambharan <jeenu.viswambharan@arm.com> | 2018-03-22 08:57:52 +0000 |
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committer | Jeenu Viswambharan <jeenu.viswambharan@arm.com> | 2018-03-26 09:45:48 +0100 |
commit | 17e84eedb2fb40d8682802cf2e23ddf67928c51d (patch) | |
tree | a91ef44ab2642507d6ffe1d39fd4fb5a2a1dd2cb /bl1 | |
parent | f13ef37a38cec17f72f08dc63bbbe546a54d78a7 (diff) |
GIC: Fix setting interrupt configuration
- Interrupt configuration is a 2-bit field, so the field shift has to
be double that of the bit number.
- Interrupt configuration (level- or edge-trigger) is specified in the
MSB of the field, not LSB.
Fixes applied to both GICv2 and GICv3 drivers.
Fixes ARM-software/tf-issues#570
Change-Id: Ia6ae6ed9ba9fb0e3eb0f921a833af48e365ba359
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
Diffstat (limited to 'bl1')
0 files changed, 0 insertions, 0 deletions