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authorDouglas Raillard <douglas.raillard@arm.com>2017-07-17 14:14:52 +0100
committerDouglas Raillard <douglas.raillard@arm.com>2017-07-24 14:17:07 +0100
commitca6b1cb4dd1f7a425ca4e8ddc670744453e6f089 (patch)
tree804aa46a5bb641587e73b8c31cf726522239073b /docs/cpu-specific-build-macros.rst
parentca5ba394cab0c4e7c5621a50a7bd270cb64cec97 (diff)
Add doc for some Cortex A53 errata workarounds
Add documentation for errata 835769 and 843419 workarounds introduced in commit a94cc374ab57b80d86974f8771565d65b38403ef Fixes ARM-software/tf-issues#504 Change-Id: I7f3db53dfc5f3827b32663f483d3302bc9679b19 Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>
Diffstat (limited to 'docs/cpu-specific-build-macros.rst')
-rw-r--r--docs/cpu-specific-build-macros.rst10
1 files changed, 10 insertions, 0 deletions
diff --git a/docs/cpu-specific-build-macros.rst b/docs/cpu-specific-build-macros.rst
index ce564a2d..5738927c 100644
--- a/docs/cpu-specific-build-macros.rst
+++ b/docs/cpu-specific-build-macros.rst
@@ -51,10 +51,20 @@ For Cortex-A53, following errata build flags are defined :
- ``ERRATA_A53_826319``: This applies errata 826319 workaround to Cortex-A53
CPU. This needs to be enabled only for revision <= r0p2 of the CPU.
+- ``ERRATA_A53_835769``: This applies erratum 835769 workaround at compile and
+ link time to Cortex-A53 CPU. This needs to be enabled for some variants of
+ revision <= r0p4. This workaround can lead the linker to create ``*.stub``
+ sections.
+
- ``ERRATA_A53_836870``: This applies errata 836870 workaround to Cortex-A53
CPU. This needs to be enabled only for revision <= r0p3 of the CPU. From
r0p4 and onwards, this errata is enabled by default in hardware.
+- ``ERRATA_A53_843419``: This applies erratum 843419 workaround at link time
+ to Cortex-A53 CPU. This needs to be enabled for some variants of revision
+ <= r0p4. This workaround can lead the linker to emit ``*.stub`` sections
+ which are 4kB aligned.
+
- ``ERRATA_A53_855873``: This applies errata 855873 workaround to Cortex-A53
CPUs. Though the erratum is present in every revision of the CPU,
this workaround is only applied to CPUs from r0p3 onwards, which feature