diff options
| author | Douglas Raillard <douglas.raillard@arm.com> | 2017-07-26 13:51:00 +0100 |
|---|---|---|
| committer | Soby Mathew <soby.mathew@arm.com> | 2017-10-05 16:47:53 +0100 |
| commit | a64b4e626ecad5d5a77dfd26c94a32c425748f4c (patch) | |
| tree | 8b1ea59fa2e8932808357b285cc39d7d72df0883 /drivers/arm | |
| parent | b50bdceadf43eea66e4539144c50eabb3bbb1c2a (diff) | |
GICv3: turn some macros into inline functions
Tidy up the code a bit by turning some macros into inline functions
which allows to remove the do/while(0) idiom and backslashes at the end
of the line.
Change-Id: Ie41a4ea4a4da507f7b925247b53e85019101d717
Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>
Diffstat (limited to 'drivers/arm')
| -rw-r--r-- | drivers/arm/gic/v3/gicv3_private.h | 48 |
1 files changed, 25 insertions, 23 deletions
diff --git a/drivers/arm/gic/v3/gicv3_private.h b/drivers/arm/gic/v3/gicv3_private.h index f95cfab6..da4bcbf7 100644 --- a/drivers/arm/gic/v3/gicv3_private.h +++ b/drivers/arm/gic/v3/gicv3_private.h @@ -22,17 +22,6 @@ #define RWP_FALSE 0 /* - * Macro to wait for updates to : - * GICD_CTLR[2:0] - the Group Enables - * GICD_CTLR[5:4] - the ARE bits - * GICD_ICENABLERn - the clearing of enable state for SPIs - */ -#define gicd_wait_for_pending_write(gicd_base) \ - do { \ - ; \ - } while (gicd_read_ctlr(gicd_base) & GICD_CTLR_RWP_BIT) - -/* * Macro to convert an mpidr to a value suitable for programming into a * GICD_IROUTER. Bits[31:24] in the MPIDR are cleared as they are not relevant * to GICv3. @@ -42,18 +31,6 @@ (irm & IROUTER_IRM_MASK) << IROUTER_IRM_SHIFT) /* - * Macro to wait for updates to : - * GICR_ICENABLER0 - * GICR_CTLR.DPG1S - * GICR_CTLR.DPG1NS - * GICR_CTLR.DPG0 - */ -#define gicr_wait_for_pending_write(gicr_base) \ - do { \ - ; \ - } while (gicr_read_ctlr(gicr_base) & GICR_CTLR_RWP_BIT) - -/* * Macro to convert a GICR_TYPER affinity value into a MPIDR value. Bits[31:24] * are zeroes. */ @@ -116,6 +93,18 @@ void gicv3_rdistif_mark_core_asleep(uintptr_t gicr_base); /******************************************************************************* * GIC Distributor interface accessors ******************************************************************************/ +/* + * Wait for updates to : + * GICD_CTLR[2:0] - the Group Enables + * GICD_CTLR[5:4] - the ARE bits + * GICD_ICENABLERn - the clearing of enable state for SPIs + */ +static inline void gicd_wait_for_pending_write(uintptr_t gicd_base) +{ + while (gicd_read_ctlr(gicd_base) & GICD_CTLR_RWP_BIT) + ; +} + static inline unsigned int gicd_read_pidr2(uintptr_t base) { return mmio_read_32(base + GICD_PIDR2_GICV3); @@ -176,6 +165,19 @@ static inline void gicr_write_waker(uintptr_t base, unsigned int val) mmio_write_32(base + GICR_WAKER, val); } +/* + * Wait for updates to : + * GICR_ICENABLER0 + * GICR_CTLR.DPG1S + * GICR_CTLR.DPG1NS + * GICR_CTLR.DPG0 + */ +static inline void gicr_wait_for_pending_write(uintptr_t gicr_base) +{ + while (gicr_read_ctlr(gicr_base) & GICR_CTLR_RWP_BIT) + ; +} + /******************************************************************************* * GIC Re-distributor functions for accessing entire registers. * Note: The raw register values correspond to multiple interrupt IDs and |