diff options
author | Yann Gautier <yann.gautier@st.com> | 2019-01-17 19:16:03 +0100 |
---|---|---|
committer | Yann Gautier <yann.gautier@st.com> | 2019-01-18 15:45:08 +0100 |
commit | c948f77136c42a92d0bb660543a3600c36dcf7f1 (patch) | |
tree | cd775e73ea2664e820bcb30c02a795d3742ab174 /fdts/stm32mp157-pinctrl.dtsi | |
parent | 23684d0e819b497d2661759b315e43e267a3a74c (diff) |
stm32mp1: update device tree files
The drivers are also updated to reflect the changes.
Set RCC as non-secure.
Change-Id: I568fa1f418355830ad1d4d1cdcdb910fb362231b
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Diffstat (limited to 'fdts/stm32mp157-pinctrl.dtsi')
-rw-r--r-- | fdts/stm32mp157-pinctrl.dtsi | 126 |
1 files changed, 99 insertions, 27 deletions
diff --git a/fdts/stm32mp157-pinctrl.dtsi b/fdts/stm32mp157-pinctrl.dtsi index 21bd34e0..9dcd7b5e 100644 --- a/fdts/stm32mp157-pinctrl.dtsi +++ b/fdts/stm32mp157-pinctrl.dtsi @@ -3,13 +3,14 @@ * Copyright (C) STMicroelectronics 2017 - All Rights Reserved * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics. */ - #include <dt-bindings/pinctrl/stm32-pinfunc.h> + / { soc { - pinctrl: pin-controller { + pinctrl: pin-controller@50002000 { #address-cells = <1>; #size-cells = <1>; + compatible = "st,stm32mp157-pinctrl"; ranges = <0 0x50002000 0xa400>; pins-are-numbered; @@ -134,54 +135,76 @@ status = "disabled"; }; - uart4_pins_a: uart4@0 { + qspi_bk1_pins_a: qspi-bk1-0 { pins1 { - pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */ + pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */ + <STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */ + <STM32_PINMUX('F', 7, AF9)>, /* QSPI_BK1_IO2 */ + <STM32_PINMUX('F', 6, AF9)>; /* QSPI_BK1_IO3 */ bias-disable; drive-push-pull; - slew-rate = <0>; + slew-rate = <1>; }; pins2 { - pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */ - bias-disable; + pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QSPI_BK1_NCS */ + bias-pull-up; + drive-push-pull; + slew-rate = <1>; }; }; - usart3_pins_a: usart3@0 { + qspi_bk2_pins_a: qspi-bk2-0 { pins1 { - pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */ - <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */ + pinmux = <STM32_PINMUX('H', 2, AF9)>, /* QSPI_BK2_IO0 */ + <STM32_PINMUX('H', 3, AF9)>, /* QSPI_BK2_IO1 */ + <STM32_PINMUX('G', 10, AF11)>, /* QSPI_BK2_IO2 */ + <STM32_PINMUX('G', 7, AF11)>; /* QSPI_BK2_IO3 */ bias-disable; drive-push-pull; - slew-rate = <0>; + slew-rate = <1>; }; pins2 { - pinmux = <STM32_PINMUX('B', 12, AF8)>, /* USART3_RX */ - <STM32_PINMUX('I', 10, AF8)>; /* USART3_CTS_NSS */ - bias-disable; + pinmux = <STM32_PINMUX('C', 0, AF10)>; /* QSPI_BK2_NCS */ + bias-pull-up; + drive-push-pull; + slew-rate = <1>; }; }; - sdmmc1_b4_pins_a: sdmmc1-b4@0 { + qspi_clk_pins_a: qspi-clk-0 { pins { + pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QSPI_CLK */ + bias-disable; + drive-push-pull; + slew-rate = <3>; + }; + }; + + sdmmc1_b4_pins_a: sdmmc1-b4-0 { + pins1 { pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */ <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */ <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */ <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */ - <STM32_PINMUX('C', 12, AF12)>, /* SDMMC1_CK */ <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */ - slew-rate = <3>; + slew-rate = <1>; + drive-push-pull; + bias-disable; + }; + pins2 { + pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */ + slew-rate = <2>; drive-push-pull; bias-disable; }; }; - sdmmc1_dir_pins_a: sdmmc1-dir@0 { + sdmmc1_dir_pins_a: sdmmc1-dir-0 { pins1 { pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */ <STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */ <STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */ - slew-rate = <3>; + slew-rate = <1>; drive-push-pull; bias-pull-up; }; @@ -191,36 +214,85 @@ }; }; - sdmmc2_b4_pins_a: sdmmc2-b4@0 { - pins { + sdmmc1_dir_pins_b: sdmmc1-dir-1 { + pins1 { + pinmux = <STM32_PINMUX('E', 12, AF8)>, /* SDMMC1_D0DIR */ + <STM32_PINMUX('E', 14, AF11)>, /* SDMMC1_D123DIR */ + <STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */ + slew-rate = <3>; + drive-push-pull; + bias-pull-up; + }; + pins2 { + pinmux = <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */ + bias-pull-up; + }; + }; + + sdmmc2_b4_pins_a: sdmmc2-b4-0 { + pins1 { pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */ <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */ <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */ <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */ - <STM32_PINMUX('E', 3, AF9)>, /* SDMMC2_CK */ <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */ - slew-rate = <3>; + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + pins2 { + pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */ + slew-rate = <2>; drive-push-pull; bias-pull-up; }; }; - sdmmc2_d47_pins_a: sdmmc2-d47@0 { + sdmmc2_d47_pins_a: sdmmc2-d47-0 { pins { pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */ <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */ <STM32_PINMUX('E', 5, AF9)>, /* SDMMC2_D6 */ <STM32_PINMUX('D', 3, AF9)>; /* SDMMC2_D7 */ - slew-rate = <3>; + slew-rate = <1>; drive-push-pull; bias-pull-up; }; }; + + uart4_pins_a: uart4-0 { + pins1 { + pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */ + bias-disable; + }; + }; + + usart3_pins_a: usart3-0 { + pins1 { + pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */ + <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('B', 12, AF8)>, /* USART3_RX */ + <STM32_PINMUX('I', 10, AF8)>; /* USART3_CTS_NSS */ + bias-disable; + }; + }; }; - pinctrl_z: pin-controller-z { + pinctrl_z: pin-controller-z@54004000 { #address-cells = <1>; #size-cells = <1>; + compatible = "st,stm32mp157-z-pinctrl"; ranges = <0 0x54004000 0x400>; pins-are-numbered; @@ -236,7 +308,7 @@ status = "disabled"; }; - i2c4_pins_a: i2c4@0 { + i2c4_pins_a: i2c4-0 { pins { pinmux = <STM32_PINMUX('Z', 4, AF6)>, /* I2C4_SCL */ <STM32_PINMUX('Z', 5, AF6)>; /* I2C4_SDA */ |