diff options
| author | Antonio Nino Diaz <antonio.ninodiaz@arm.com> | 2017-09-14 15:57:44 +0100 |
|---|---|---|
| committer | Antonio Nino Diaz <antonio.ninodiaz@arm.com> | 2017-09-21 12:03:53 +0100 |
| commit | e47ac1fd634a3934d7d3ac446190b2f4bd8a640f (patch) | |
| tree | 4291bffc8b34a4d395bbee467ee5fcaff2bcdbeb /include/drivers | |
| parent | df312c5a2b152953f755df9d979cff20afb7ef4b (diff) | |
Fix type of `unsigned long` constants
The type `unsigned long` is 32 bit wide in AArch32, but 64 bit wide in
AArch64. This is inconsistent and that's why we avoid using it as per
the Coding Guidelines. This patch changes all `UL` occurrences to `U`
or `ULL` depending on the context so that the size of the constant is
clear.
This problem affected the macro `BIT(nr)`. As long as this macro is used
to fill fields of registers, that's not a problem, since all registers
are 32 bit wide in AArch32 and 64 bit wide in AArch64. However, if the
macro is used to fill the fields of a 64-bit integer, it won't be able
to set the upper 32 bits in AArch32.
By changing the type of this macro to `unsigned long long` the behaviour
is always the same regardless of the architecture, as this type is
64-bit wide in both cases.
Some Tegra platform files have been modified by this patch.
Change-Id: I918264c03e7d691a931f0d1018df25a2796cc221
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Diffstat (limited to 'include/drivers')
| -rw-r--r-- | include/drivers/arm/gic_v3.h | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/include/drivers/arm/gic_v3.h b/include/drivers/arm/gic_v3.h index ee8f26be..02f9006f 100644 --- a/include/drivers/arm/gic_v3.h +++ b/include/drivers/arm/gic_v3.h @@ -26,17 +26,17 @@ #define GICR_WAKER 0x14 /* GICR_WAKER bit definitions */ -#define WAKER_CA (1UL << 2) -#define WAKER_PS (1UL << 1) +#define WAKER_CA (U(1) << 2) +#define WAKER_PS (U(1) << 1) /* GICR_TYPER bit definitions */ #define GICR_TYPER_AFF_SHIFT 32 #define GICR_TYPER_AFF_MASK 0xffffffff -#define GICR_TYPER_LAST (1UL << 4) +#define GICR_TYPER_LAST (U(1) << 4) /* GICv3 ICC_SRE register bit definitions*/ -#define ICC_SRE_EN (1UL << 3) -#define ICC_SRE_SRE (1UL << 0) +#define ICC_SRE_EN (U(1) << 3) +#define ICC_SRE_SRE (U(1) << 0) /******************************************************************************* * GICv3 defintions |