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authorNishanth Menon <nm@ti.com>2017-01-10 09:34:07 -0600
committerNishanth Menon <nm@ti.com>2017-01-10 09:36:44 -0600
commit861ac52a7e80c0399b6e543e7125a9c1e18a63f8 (patch)
tree4d735faceb0449e4de072adc56e60e88d105a69f /include/drivers
parent176129530e80491a789ea6402a18b65834c7fe54 (diff)
uart: 16550: Fix getc
tbz check for RDR status is to check for a bit being zero. Unfortunately, we are using a mask rather than the bit position. Further as per http://www.ti.com/lit/ds/symlink/pc16550d.pdf (page 17), LSR register bit 0 is Data ready status (RDR), not bit position 2. Update the same to match the specification. Reported-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
Diffstat (limited to 'include/drivers')
-rw-r--r--include/drivers/ti/uart/uart_16550.h3
1 files changed, 2 insertions, 1 deletions
diff --git a/include/drivers/ti/uart/uart_16550.h b/include/drivers/ti/uart/uart_16550.h
index 2c814ef2..773e2f16 100644
--- a/include/drivers/ti/uart/uart_16550.h
+++ b/include/drivers/ti/uart/uart_16550.h
@@ -88,6 +88,7 @@
#define UARTLSR_FERR (1 << 3) /* Framing Error */
#define UARTLSR_PERR (1 << 3) /* Parity Error */
#define UARTLSR_OVRF (1 << 2) /* Rx Overrun Error */
-#define UARTLSR_RDR (1 << 2) /* Rx Data Ready */
+#define UARTLSR_RDR_BIT (0) /* Rx Data Ready Bit */
+#define UARTLSR_RDR (1 << UARTLSR_RDR_BIT) /* Rx Data Ready */
#endif /* __UART_16550_H__ */