diff options
| author | Soby Mathew <soby.mathew@arm.com> | 2019-05-01 09:43:18 +0100 |
|---|---|---|
| committer | Soby Mathew <soby.mathew@arm.com> | 2019-05-07 13:46:47 +0100 |
| commit | e6e1d0ac162027334471e1eb9f1e0ce46065db6a (patch) | |
| tree | fbc4be5d69c1395bf512be97e9adfebac5a187d9 /include/lib | |
| parent | 8917380a1eba4f7a499a4a51b75a0488a683d2c0 (diff) | |
Cortex-A76: workarounds for errata 1257314, 1262606, 1262888, 1275112
The workarounds for errata 1257314, 1262606, 1262888 and 1275112 are
added to the Cortex-A76 cpu specific file. The workarounds are disabled
by default and have to be explicitly enabled by the platform integrator.
Change-Id: I70474927374cb67725f829d159ddde9ac4edc343
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
Diffstat (limited to 'include/lib')
| -rw-r--r-- | include/lib/cpus/aarch64/cortex_a76.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/include/lib/cpus/aarch64/cortex_a76.h b/include/lib/cpus/aarch64/cortex_a76.h index c2af8cad..7dc7e068 100644 --- a/include/lib/cpus/aarch64/cortex_a76.h +++ b/include/lib/cpus/aarch64/cortex_a76.h @@ -19,6 +19,7 @@ #define CORTEX_A76_CPUECTLR_EL1 S3_0_C15_C1_4 #define CORTEX_A76_CPUECTLR_EL1_WS_THR_L2 (ULL(3) << 24) +#define CORTEX_A76_CPUECTLR_EL1_BIT_51 (ULL(1) << 51) /******************************************************************************* * CPU Auxiliary Control register specific definitions. @@ -27,10 +28,17 @@ #define CORTEX_A76_CPUACTLR_EL1_DISABLE_STATIC_PREDICTION (ULL(1) << 6) +#define CORTEX_A76_CPUACTLR_EL1_BIT_13 (ULL(1) << 13) + #define CORTEX_A76_CPUACTLR2_EL1 S3_0_C15_C1_1 #define CORTEX_A76_CPUACTLR2_EL1_DISABLE_LOAD_PASS_STORE (ULL(1) << 16) +#define CORTEX_A76_CPUACTLR3_EL1 S3_0_C15_C1_2 + +#define CORTEX_A76_CPUACTLR3_EL1_BIT_10 (ULL(1) << 10) + + /* Definitions of register field mask in CORTEX_A76_CPUPWRCTLR_EL1 */ #define CORTEX_A76_CORE_PWRDN_EN_MASK U(0x1) |