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authorJuan Castillo <juan.castillo@arm.com>2015-11-16 16:53:38 +0000
committerJuan Castillo <juan.castillo@arm.com>2015-12-10 09:22:44 +0000
commit12f654b6a88f6f927fe34d00eece537b01f444e3 (patch)
treec73cfddac689a1b0a1827ae2687a30bd08e2a2ce /include
parentf3974ea5b17b0ec88091a8a8c59e56da0fe507f0 (diff)
De-feature PL011 UART driver to match generic UART spec
The Server Base System Architecture document (ARM-DEN-0029) specifies a generic UART device. The programmer's view of this generic UART is a subset of the ARM PL011 UART. However, the current PL011 driver in Trusted Firmware uses some features that are outside the generic UART specification. This patch modifies the PL011 driver to exclude features outside the SBSA generic UART specification by setting the boolean build option 'PL011_GENERIC_UART=1'. Default value is 0 (use full PL011 features). User guide updated. Fixes ARM-software/tf-issues#216 Change-Id: I6e0eb86f9d69569bc3980fb57e70d6da5d91a737
Diffstat (limited to 'include')
-rw-r--r--include/drivers/arm/pl011.h13
1 files changed, 10 insertions, 3 deletions
diff --git a/include/drivers/arm/pl011.h b/include/drivers/arm/pl011.h
index 7c4df621..d5ea890d 100644
--- a/include/drivers/arm/pl011.h
+++ b/include/drivers/arm/pl011.h
@@ -36,17 +36,21 @@
#define UARTRSR 0x004
#define UARTECR 0x004
#define UARTFR 0x018
+#define UARTIMSC 0x038
+#define UARTRIS 0x03C
+#define UARTICR 0x044
+
+/* PL011 registers (out of the SBSA specification) */
+#if !PL011_GENERIC_UART
#define UARTILPR 0x020
#define UARTIBRD 0x024
#define UARTFBRD 0x028
#define UARTLCR_H 0x02C
#define UARTCR 0x030
#define UARTIFLS 0x034
-#define UARTIMSC 0x038
-#define UARTRIS 0x03C
#define UARTMIS 0x040
-#define UARTICR 0x044
#define UARTDMACR 0x048
+#endif /* !PL011_GENERIC_UART */
/* Data status bits */
#define UART_DATA_ERROR_MASK 0x0F00
@@ -69,6 +73,7 @@
#define PL011_UARTFR_RXFE_BIT 4 /* Receive FIFO empty bit in UARTFR register */
/* Control reg bits */
+#if !PL011_GENERIC_UART
#define PL011_UARTCR_CTSEN (1 << 15) /* CTS hardware flow control enable */
#define PL011_UARTCR_RTSEN (1 << 14) /* RTS hardware flow control enable */
#define PL011_UARTCR_RTS (1 << 11) /* Request to send */
@@ -95,4 +100,6 @@
#define PL011_UARTLCR_H_PEN (1 << 1) /* Parity Enable */
#define PL011_UARTLCR_H_BRK (1 << 0) /* Send break */
+#endif /* !PL011_GENERIC_UART */
+
#endif /* __PL011_H__ */