diff options
| author | Louis Mayencourt <louis.mayencourt@arm.com> | 2019-02-25 14:57:57 +0000 |
|---|---|---|
| committer | Louis Mayencourt <louis.mayencourt@arm.com> | 2019-02-26 16:20:59 +0000 |
| commit | 98551591f5371de2c2f0dee6be2e12b75653f04d (patch) | |
| tree | 8d894f2bf5d5e3ec7d29ca270169c2c37457e814 /lib/cpus | |
| parent | 5f5d1ed7d5a7626b2da48f3ac423d366bbee1fd8 (diff) | |
Add workaround for errata 790748 for Cortex-A75
Internal timing conditions might cause the CPU to stop processing
interrupts. Set bit 13 of CPUACTLR_EL1 to prevent this.
Change-Id: Ifdd19dbcdb71bb0d9609cab1315c478aaedb03ba
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
Diffstat (limited to 'lib/cpus')
| -rw-r--r-- | lib/cpus/aarch64/cortex_a75.S | 36 | ||||
| -rw-r--r-- | lib/cpus/cpu-ops.mk | 8 |
2 files changed, 44 insertions, 0 deletions
diff --git a/lib/cpus/aarch64/cortex_a75.S b/lib/cpus/aarch64/cortex_a75.S index 8d04294d..20401889 100644 --- a/lib/cpus/aarch64/cortex_a75.S +++ b/lib/cpus/aarch64/cortex_a75.S @@ -38,6 +38,34 @@ func check_errata_764081 b cpu_rev_var_ls endfunc check_errata_764081 + /* -------------------------------------------------- + * Errata Workaround for Cortex A75 Errata #790748. + * This applies only to revision r0p0 of Cortex A75. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x17 + * -------------------------------------------------- + */ +func errata_a75_790748_wa + /* + * Compare x0 against revision r0p0 + */ + mov x17, x30 + bl check_errata_790748 + cbz x0, 1f + mrs x1, CORTEX_A75_CPUACTLR_EL1 + orr x1, x1 ,#(1 << 13) + msr CORTEX_A75_CPUACTLR_EL1, x1 + isb +1: + ret x17 +endfunc errata_a75_790748_wa + +func check_errata_790748 + mov x1, #0x00 + b cpu_rev_var_ls +endfunc check_errata_790748 + /* ------------------------------------------------- * The CPU Ops reset function for Cortex-A75. * ------------------------------------------------- @@ -45,11 +73,18 @@ endfunc check_errata_764081 func cortex_a75_reset_func mov x19, x30 bl cpu_get_rev_var + mov x18, x0 #if ERRATA_A75_764081 + mov x0, x18 bl errata_a75_764081_wa #endif +#if ERRATA_A75_790748 + mov x0, x18 + bl errata_a75_790748_wa +#endif + #if IMAGE_BL31 && WORKAROUND_CVE_2017_5715 cpu_check_csv2 x0, 1f adr x0, wa_cve_2017_5715_bpiall_vbar @@ -148,6 +183,7 @@ func cortex_a75_errata_report * checking functions of each errata. */ report_errata ERRATA_A75_764081, cortex_a75, 764081 + report_errata ERRATA_A75_790748, cortex_a75, 790748 report_errata WORKAROUND_CVE_2017_5715, cortex_a75, cve_2017_5715 report_errata WORKAROUND_CVE_2018_3639, cortex_a75, cve_2018_3639 report_errata ERRATA_DSU_936184, cortex_a75, dsu_936184 diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index be7d3bde..a7acd2f8 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -127,6 +127,10 @@ ERRATA_A73_855423 ?=0 # only to revision <= r0p0 of the Cortex A75 cpu. ERRATA_A75_764081 ?=0 +# Flag to apply erratum 790748 workaround during reset. This erratum applies +# only to revision <= r0p0 of the Cortex A75 cpu. +ERRATA_A75_790748 ?=0 + # Flag to apply T32 CLREX workaround during reset. This erratum applies # only to r0p0 and r1p0 of the Neoverse N1 cpu. ERRATA_N1_1043202 ?=1 @@ -204,6 +208,10 @@ $(eval $(call add_define,ERRATA_A73_855423)) $(eval $(call assert_boolean,ERRATA_A75_764081)) $(eval $(call add_define,ERRATA_A75_764081)) +# Process ERRATA_A75_790748 flag +$(eval $(call assert_boolean,ERRATA_A75_790748)) +$(eval $(call add_define,ERRATA_A75_790748)) + # Process ERRATA_N1_1043202 flag $(eval $(call assert_boolean,ERRATA_N1_1043202)) $(eval $(call add_define,ERRATA_N1_1043202)) |