diff options
| author | Anson Huang <Anson.Huang@nxp.com> | 2017-08-04 18:29:23 +0800 |
|---|---|---|
| committer | Abel Vesa <abel.vesa@nxp.com> | 2018-06-11 10:08:39 +0300 |
| commit | aabf9533ef1008f92b65be0608d380d5a513f983 (patch) | |
| tree | 1f01f922863db655a91c0eaf5210d22be687971a /plat/imx/imx8mq | |
| parent | 5c96de72ce1609c4520025ffc5bf178e1279cb55 (diff) | |
imx8mq: enable all PUs power until all PUs power on/off function ready
As there are too many difference between each PU's power
on/off flow, here enable all PUs power until all modules'
power on/off function ready and tested, then we will enable
this PU PGC feature.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Diffstat (limited to 'plat/imx/imx8mq')
| -rw-r--r-- | plat/imx/imx8mq/gpc.c | 2 | ||||
| -rw-r--r-- | plat/imx/imx8mq/imx8m_bl31_setup.c | 4 |
2 files changed, 6 insertions, 0 deletions
diff --git a/plat/imx/imx8mq/gpc.c b/plat/imx/imx8mq/gpc.c index ea4fbb0a..96848f1d 100644 --- a/plat/imx/imx8mq/gpc.c +++ b/plat/imx/imx8mq/gpc.c @@ -444,6 +444,8 @@ static void imx_gpc_pm_domain_enable(uint32_t domain_id, uint32_t on) uint32_t val; uintptr_t reg; + return; + /* * PCIE1 and PCIE2 share the same reset signal, if we power down * PCIE2, PCIE1 will be hold in reset too. diff --git a/plat/imx/imx8mq/imx8m_bl31_setup.c b/plat/imx/imx8mq/imx8m_bl31_setup.c index ac5067b2..5b11beed 100644 --- a/plat/imx/imx8mq/imx8m_bl31_setup.c +++ b/plat/imx/imx8mq/imx8m_bl31_setup.c @@ -171,6 +171,10 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, mmio_write_32(0x32df004c, 0x0); mmio_write_32(0x32df0050, 0x0); + mmio_write_32(0x303a00ec, 0x0000ffff); + /* Power up VPU, DISP, GPU etc */ + mmio_write_32(0x303a00f8, 0x3fef); + #if DEBUG_CONSOLE console_init(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ, IMX_CONSOLE_BAUDRATE); |