diff options
| author | Paul Beesley <paul.beesley@arm.com> | 2019-08-28 13:05:51 +0000 |
|---|---|---|
| committer | TrustedFirmware Code Review <review@review.trustedfirmware.org> | 2019-08-28 13:05:51 +0000 |
| commit | 3441952f61a62948ccf84c2e3eada9b340c3560d (patch) | |
| tree | 3c16d37e50b091ccd574f28a9ca28bae65610638 /plat/intel | |
| parent | de58048830364a749d0ebb612e15c1c9a2cb435c (diff) | |
| parent | 960a12b3fb4699cad83973c853fb5064ed6a75d0 (diff) | |
Merge "intel: agilex: Clear PLL lostlock bypass mode" into integration
Diffstat (limited to 'plat/intel')
| -rw-r--r-- | plat/intel/soc/agilex/include/agilex_clock_manager.h | 3 | ||||
| -rw-r--r-- | plat/intel/soc/agilex/soc/agilex_clock_manager.c | 10 |
2 files changed, 13 insertions, 0 deletions
diff --git a/plat/intel/soc/agilex/include/agilex_clock_manager.h b/plat/intel/soc/agilex/include/agilex_clock_manager.h index 73e6c4e1..0822290a 100644 --- a/plat/intel/soc/agilex/include/agilex_clock_manager.h +++ b/plat/intel/soc/agilex/include/agilex_clock_manager.h @@ -33,6 +33,7 @@ #define CLKMGR_MAINPLL_PLLC2 0x40 #define CLKMGR_MAINPLL_PLLC3 0x44 #define CLKMGR_MAINPLL_PLLM 0x48 +#define CLKMGR_MAINPLL_LOSTLOCK 0x54 /* Peripheral PLL Group */ #define CLKMGR_PERPLL 0xffd1007c @@ -50,6 +51,7 @@ #define CLKMGR_PERPLL_PLLC2 0x3c #define CLKMGR_PERPLL_PLLC3 0x40 #define CLKMGR_PERPLL_PLLM 0x44 +#define CLKMGR_PERPLL_LOSTLOCK 0x50 /* Altera Group */ #define CLKMGR_ALTERA 0xffd100d0 @@ -112,6 +114,7 @@ #define CLKMGR_VCOCALIB_HSCNT_SET(x) (((x) << 0) & 0x000003ff) #define CLKMGR_VCOCALIB_MSCNT_SET(x) (((x) << 16) & 0x00ff0000) +#define CLKMGR_CLR_LOSTLOCK_BYPASS 0x20000000 typedef struct { uint32_t clk_freq_of_eosc1; diff --git a/plat/intel/soc/agilex/soc/agilex_clock_manager.c b/plat/intel/soc/agilex/soc/agilex_clock_manager.c index 218676a9..06891ff9 100644 --- a/plat/intel/soc/agilex/soc/agilex_clock_manager.c +++ b/plat/intel/soc/agilex/soc/agilex_clock_manager.c @@ -222,6 +222,16 @@ void config_clkmgr_handoff(handoff *hoff_ptr) mmio_write_32(CLKMGR_ALTERA + CLKMGR_ALTERA_PSIREFCTR, hoff_ptr->alt_psirefctr); + /* Clear lost lock bypass mode */ + mmio_write_32(CLKMGR_MAINPLL + CLKMGR_MAINPLL_LOSTLOCK, 0x1); + mmio_write_32(CLKMGR_PERPLL + CLKMGR_PERPLL_LOSTLOCK, 0x1); + + mmio_setbits_32(CLKMGR_MAINPLL + CLKMGR_MAINPLL_PLLGLOB, + CLKMGR_CLR_LOSTLOCK_BYPASS); + + mmio_setbits_32(CLKMGR_PERPLL + CLKMGR_PERPLL_PLLGLOB, + CLKMGR_CLR_LOSTLOCK_BYPASS); + /* Take all PLLs out of bypass */ mmio_write_32(CLKMGR_MAINPLL + CLKMGR_MAINPLL_BYPASS, 0); wait_fsm(); |