diff options
| author | Varun Wadekar <vwadekar@nvidia.com> | 2017-06-28 14:38:19 -0700 |
|---|---|---|
| committer | Varun Wadekar <vwadekar@nvidia.com> | 2019-01-18 09:21:50 -0800 |
| commit | 647d4a035a3a4649dc218f2a42f34d07d371c336 (patch) | |
| tree | 1b87235500621be0379f1524dc1084c400cfdddf /plat/nvidia/tegra/include | |
| parent | 76a7cd334666b069c6a48158450faa44df1f1c88 (diff) | |
Tegra: gpcdma: driver for general purpose DMA
This patch adds the driver for the general purpose DMA hardware
block on newer Tegra SoCs. The GPCDMA is a special purpose DMA
used to speed up memory copy operations to/from DRAM and TZSRAM.
This patch introduces a macro 'USE_GPC_DMA' to allow platforms
to override CPU based memory operations.
Change-Id: I3170d409c83b77e785437b1002a8d70188fabbeb
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Diffstat (limited to 'plat/nvidia/tegra/include')
| -rw-r--r-- | plat/nvidia/tegra/include/drivers/gpcdma.h | 16 | ||||
| -rw-r--r-- | plat/nvidia/tegra/include/t186/tegra_def.h | 7 |
2 files changed, 23 insertions, 0 deletions
diff --git a/plat/nvidia/tegra/include/drivers/gpcdma.h b/plat/nvidia/tegra/include/drivers/gpcdma.h new file mode 100644 index 00000000..fb5486a8 --- /dev/null +++ b/plat/nvidia/tegra/include/drivers/gpcdma.h @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __GPCDMA_H__ +#define __GPCDMA_H__ + +#include <stdint.h> + +void tegra_gpcdma_memcpy(uint64_t dst_addr, uint64_t src_addr, + uint32_t num_bytes); +void tegra_gpcdma_zeromem(uint64_t dst_addr, uint32_t num_bytes); + +#endif /* __GPCDMA_H__ */ diff --git a/plat/nvidia/tegra/include/t186/tegra_def.h b/plat/nvidia/tegra/include/t186/tegra_def.h index 3abba551..9bc95c1c 100644 --- a/plat/nvidia/tegra/include/t186/tegra_def.h +++ b/plat/nvidia/tegra/include/t186/tegra_def.h @@ -116,6 +116,11 @@ #define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU (U(0) << 11) /******************************************************************************* + * Tegra General Purpose Centralised DMA constants + ******************************************************************************/ +#define TEGRA_GPCDMA_BASE U(0x2610000) + +/******************************************************************************* * Tegra Memory Controller constants ******************************************************************************/ #define TEGRA_MC_STREAMID_BASE U(0x02C00000) @@ -198,6 +203,8 @@ #define TEGRA_CAR_RESET_BASE U(0x05000000) #define TEGRA_GPU_RESET_REG_OFFSET U(0x30) #define GPU_RESET_BIT (U(1) << 0) +#define TEGRA_GPCDMA_RST_SET_REG_OFFSET U(0x6A0004) +#define TEGRA_GPCDMA_RST_CLR_REG_OFFSET U(0x6A0008) /******************************************************************************* * Tegra micro-seconds timer constants |