diff options
| author | kalyani chidambaram <kalyanic@nvidia.com> | 2018-03-06 16:36:57 -0800 |
|---|---|---|
| committer | Varun Wadekar <vwadekar@nvidia.com> | 2019-01-31 08:49:05 -0800 |
| commit | fdc08e2ecbc18ca70001ccf1fe064a3625d36b5b (patch) | |
| tree | 25688cec02df99004daeaadc8537103bcb364eaf /plat/nvidia/tegra/include | |
| parent | 2d5560f928544f375c9e757d3a271bac980c0bef (diff) | |
Tegra210: SiP handlers to allow PMC access
This patch adds SiP handler for Tegra210 platforms to service
read/write requests for PMC block. None of the secure registers
are accessible to the NS world though.
Change-Id: I7dc1f10c6a6ee6efc642ddcfb1170fb36d3accff
Signed-off-by: kalyani chidambaram <kalyanic@nvidia.com>
Diffstat (limited to 'plat/nvidia/tegra/include')
| -rw-r--r-- | plat/nvidia/tegra/include/drivers/pmc.h | 11 | ||||
| -rw-r--r-- | plat/nvidia/tegra/include/t210/tegra_def.h | 1 |
2 files changed, 12 insertions, 0 deletions
diff --git a/plat/nvidia/tegra/include/drivers/pmc.h b/plat/nvidia/tegra/include/drivers/pmc.h index 53317de1..c376440f 100644 --- a/plat/nvidia/tegra/include/drivers/pmc.h +++ b/plat/nvidia/tegra/include/drivers/pmc.h @@ -14,18 +14,29 @@ #include <tegra_def.h> #define PMC_CONFIG U(0x0) +#define PMC_DPD_ENABLE_0 U(0x24) #define PMC_PWRGATE_STATUS U(0x38) #define PMC_PWRGATE_TOGGLE U(0x30) +#define PMC_SECURE_SCRATCH0 U(0xb0) +#define PMC_SECURE_SCRATCH5 U(0xc4) +#define PMC_CRYPTO_OP_0 U(0xf4) #define PMC_TOGGLE_START U(0x100) #define PMC_SCRATCH39 U(0x138) +#define PMC_SECURE_SCRATCH6 U(0x224) +#define PMC_SECURE_SCRATCH7 U(0x228) #define PMC_SECURE_DISABLE2 U(0x2c4) #define PMC_SECURE_DISABLE2_WRITE22_ON (U(1) << 28) +#define PMC_SECURE_SCRATCH8 U(0x300) +#define PMC_SECURE_SCRATCH79 U(0x41c) +#define PMC_FUSE_CONTROL_0 U(0x450) #define PMC_SECURE_SCRATCH22 U(0x338) #define PMC_SECURE_DISABLE3 U(0x2d8) #define PMC_SECURE_DISABLE3_WRITE34_ON (U(1) << 20) #define PMC_SECURE_DISABLE3_WRITE35_ON (U(1) << 22) #define PMC_SECURE_SCRATCH34 U(0x368) #define PMC_SECURE_SCRATCH35 U(0x36c) +#define PMC_SECURE_SCRATCH80 U(0xa98) +#define PMC_SECURE_SCRATCH119 U(0xb34) #define PMC_SCRATCH201 U(0x844) static inline uint32_t tegra_pmc_read_32(uint32_t off) diff --git a/plat/nvidia/tegra/include/t210/tegra_def.h b/plat/nvidia/tegra/include/t210/tegra_def.h index eed443d1..0f24f324 100644 --- a/plat/nvidia/tegra/include/t210/tegra_def.h +++ b/plat/nvidia/tegra/include/t210/tegra_def.h @@ -196,6 +196,7 @@ * Tegra Power Mgmt Controller constants ******************************************************************************/ #define TEGRA_PMC_BASE U(0x7000E400) +#define TEGRA_PMC_SIZE U(0xC00) /* 3k */ /******************************************************************************* * Tegra Atomics constants |