diff options
| author | Varun Wadekar <vwadekar@nvidia.com> | 2018-01-02 14:10:18 -0800 |
|---|---|---|
| committer | Varun Wadekar <vwadekar@nvidia.com> | 2019-01-31 08:45:41 -0800 |
| commit | 8510376c26449b45973821f226d180c19a30a1e0 (patch) | |
| tree | 3ba1adb255932b29129ed0bad10dded55cb1deb4 /plat/nvidia | |
| parent | 0887026ec149e8801c2ac14725d5151db836f8a8 (diff) | |
Tegra: fix offset used to dump GICD registers from crash handler
The GICD registers are 32-bits wide whereas the crash handler was reading
them as 64-bit ones. This patch fixes the code to read the GICD registers,
32-bits at a time, from the paltform's crash handler.
Change-Id: If3d6608529684ecc02be6a1b715012310813b2a4
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Diffstat (limited to 'plat/nvidia')
| -rw-r--r-- | plat/nvidia/tegra/include/plat_macros.S | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/plat/nvidia/tegra/include/plat_macros.S b/plat/nvidia/tegra/include/plat_macros.S index 01ae821e..2796c5d2 100644 --- a/plat/nvidia/tegra/include/plat_macros.S +++ b/plat/nvidia/tegra/include/plat_macros.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -50,7 +50,7 @@ spacer: bl asm_print_hex adr x4, spacer bl asm_print_str - ldr x4, [x7], #8 + ldr w4, [x7], #4 bl asm_print_hex adr x4, newline bl asm_print_str |