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authorAndrew F. Davis <afd@ti.com>2018-07-26 14:25:03 -0500
committerAndrew F. Davis <afd@ti.com>2018-07-26 14:31:06 -0500
commit903f13d312dfc743c1df41edb9865bd017a0eec6 (patch)
tree7ef0ac07bbf860a066706c412f7a2c8420efa0d3 /plat/ti
parent9262eb54db167d432fe0856b5451039a1b948f6f (diff)
ti: k3: common: Only enable caches early
We can enter and exit coherency without any software operations, but HW_ASSISTED_COHERENCY has stronger implications that are causing issues. Until these can be resolved, only use the weaker WARMBOOT_ENABLE_DCACHE_EARLY flag. Signed-off-by: Andrew F. Davis <afd@ti.com>
Diffstat (limited to 'plat/ti')
-rw-r--r--plat/ti/k3/common/plat_common.mk2
1 files changed, 1 insertions, 1 deletions
diff --git a/plat/ti/k3/common/plat_common.mk b/plat/ti/k3/common/plat_common.mk
index bf2a73fb..7cb6eb78 100644
--- a/plat/ti/k3/common/plat_common.mk
+++ b/plat/ti/k3/common/plat_common.mk
@@ -12,7 +12,7 @@ COLD_BOOT_SINGLE_CPU := 1
PROGRAMMABLE_RESET_ADDRESS:= 1
# System coherency is managed in hardware
-HW_ASSISTED_COHERENCY := 1
+WARMBOOT_ENABLE_DCACHE_EARLY:= 1
USE_COHERENT_MEM := 0
ERROR_DEPRECATED := 1