diff options
author | Caesar Wang <wxt@rock-chips.com> | 2017-06-28 08:40:26 +0800 |
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committer | Caesar Wang <wxt@rock-chips.com> | 2017-06-28 08:40:26 +0800 |
commit | dea1e8ee8008c58fbbbf63ff1093bf1c98c77c4d (patch) | |
tree | d5ec947b57791d2d581d069509144d1a800b3287 /plat | |
parent | 2fee1b0c4db29a26f7e3b9fb4aece5d5b591feda (diff) |
rockchip: enable A53's erratum 855873 for rk3399
For rk3399, the L2ACTLR[14] is 0 by default, as ACE CCI-500 doesn't
support WriteEvict. and you will hit the condition L2ACTLR[3] with 0,
as the Evict transactions should propagate to CCI-500 since it has
snoop filters.
Maybe this erratum applies to all Cortex-A53 cores so far, especially
if RK3399's A53 is a r0p4. we should enable it to avoid data corruption,
Change-Id: Ib86933f1fc84f8919c8e43dac41af60fd0c3ce2f
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Diffstat (limited to 'plat')
-rw-r--r-- | plat/rockchip/rk3399/platform.mk | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/plat/rockchip/rk3399/platform.mk b/plat/rockchip/rk3399/platform.mk index cb7999b5..61071243 100644 --- a/plat/rockchip/rk3399/platform.mk +++ b/plat/rockchip/rk3399/platform.mk @@ -65,6 +65,9 @@ ENABLE_PLAT_COMPAT := 0 $(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT)) +# Enable workarounds for selected Cortex-A53 erratas. +ERRATA_A53_855873 := 1 + # M0 source build PLAT_M0 := ${PLAT}m0 BUILD_M0 := ${BUILD_PLAT}/m0 |