diff options
| -rw-r--r-- | plat/allwinner/common/sunxi_bl31_setup.c | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/plat/allwinner/common/sunxi_bl31_setup.c b/plat/allwinner/common/sunxi_bl31_setup.c index 8f597c39..2c663291 100644 --- a/plat/allwinner/common/sunxi_bl31_setup.c +++ b/plat/allwinner/common/sunxi_bl31_setup.c @@ -11,6 +11,7 @@ #include <generic_delay_timer.h> #include <gicv2.h> #include <libfdt.h> +#include <mmio.h> #include <platform.h> #include <platform_def.h> #include <sunxi_def.h> @@ -148,6 +149,25 @@ void bl31_platform_setup(void) sunxi_security_setup(); + /* + * On the A64 U-Boot's SPL sets the bus clocks to some conservative + * values, to work around FEL mode instabilities with SRAM C accesses. + * FEL mode is gone when we reach ATF, so bring the AHB1 bus + * (the "main" bus) clock frequency back to the recommended 200MHz, + * for improved performance. + */ + if (soc_id == SUNXI_SOC_A64) + mmio_write_32(SUNXI_CCU_BASE + 0x54, 0x00003180); + + /* + * U-Boot or the kernel don't setup AHB2, which leaves it at the + * AHB1 frequency (200 MHz, see above). However Allwinner recommends + * 300 MHz, for improved Ethernet and USB performance. Switch the + * clock to use "PLL_PERIPH0 / 2". + */ + if (soc_id == SUNXI_SOC_A64 || soc_id == SUNXI_SOC_H5) + mmio_write_32(SUNXI_CCU_BASE + 0x5c, 0x1); + sunxi_pmic_setup(soc_id, fdt); INFO("BL31: Platform setup done\n"); |