diff options
| -rw-r--r-- | bl1/bl1.mk | 5 | ||||
| -rw-r--r-- | bl2/bl2.mk | 7 | ||||
| -rw-r--r-- | bl31/bl31.mk | 1 | ||||
| -rw-r--r-- | docs/cpu-specific-build-macros.rst | 33 | ||||
| -rw-r--r-- | docs/user-guide.rst | 5 | ||||
| -rw-r--r-- | include/lib/cpus/aarch64/dsu_def.h | 33 | ||||
| -rw-r--r-- | lib/cpus/aarch64/cortex_a55.S | 32 | ||||
| -rw-r--r-- | lib/cpus/aarch64/cortex_a75.S | 8 | ||||
| -rw-r--r-- | lib/cpus/aarch64/cortex_a76.S | 10 | ||||
| -rw-r--r-- | lib/cpus/aarch64/denver.S | 60 | ||||
| -rw-r--r-- | lib/cpus/aarch64/dsu_helpers.S | 60 | ||||
| -rw-r--r-- | lib/cpus/cpu-ops.mk | 9 | ||||
| -rw-r--r-- | plat/arm/board/common/board_common.mk | 10 | ||||
| -rw-r--r-- | plat/arm/board/fvp/platform.mk | 7 | ||||
| -rw-r--r-- | plat/arm/board/juno/platform.mk | 7 | ||||
| -rw-r--r-- | plat/arm/board/sgi575/platform.mk | 7 | ||||
| -rw-r--r-- | plat/arm/board/sgm775/platform.mk | 7 | ||||
| -rw-r--r-- | plat/rockchip/common/aarch64/plat_helpers.S | 7 | ||||
| -rw-r--r-- | plat/rpi3/include/platform_def.h | 5 | ||||
| -rw-r--r-- | plat/rpi3/platform.mk | 2 | ||||
| -rw-r--r-- | plat/rpi3/rpi3_bl2_setup.c | 6 | ||||
| -rw-r--r-- | plat/rpi3/rpi3_bl31_setup.c | 18 |
22 files changed, 293 insertions, 46 deletions
@@ -1,5 +1,5 @@ # -# Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -17,7 +17,8 @@ BL1_SOURCES += bl1/bl1_main.c \ ${MBEDTLS_SOURCES} ifeq (${ARCH},aarch64) -BL1_SOURCES += lib/el3_runtime/aarch64/context.S +BL1_SOURCES += lib/cpus/aarch64/dsu_helpers.S \ + lib/el3_runtime/aarch64/context.S endif ifeq (${TRUSTED_BOARD_BOOT},1) @@ -1,5 +1,5 @@ # -# Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -29,5 +29,10 @@ BL2_SOURCES += bl2/${ARCH}/bl2_el3_entrypoint.S \ bl2/${ARCH}/bl2_el3_exceptions.S \ lib/cpus/${ARCH}/cpu_helpers.S \ lib/cpus/errata_report.c + +ifeq (${ARCH},aarch64) +BL2_SOURCES += lib/cpus/aarch64/dsu_helpers.S +endif + BL2_LINKERFILE := bl2/bl2_el3.ld.S endif diff --git a/bl31/bl31.mk b/bl31/bl31.mk index c99b637d..77779548 100644 --- a/bl31/bl31.mk +++ b/bl31/bl31.mk @@ -24,6 +24,7 @@ BL31_SOURCES += bl31/bl31_main.c \ bl31/bl31_context_mgmt.c \ common/runtime_svc.c \ lib/aarch64/setjmp.S \ + lib/cpus/aarch64/dsu_helpers.S \ plat/common/aarch64/platform_mp_stack.S \ services/arm_arch_svc/arm_arch_svc_setup.c \ services/std_svc/std_svc_setup.c \ diff --git a/docs/cpu-specific-build-macros.rst b/docs/cpu-specific-build-macros.rst index c11f6403..151c99e9 100644 --- a/docs/cpu-specific-build-macros.rst +++ b/docs/cpu-specific-build-macros.rst @@ -68,10 +68,10 @@ In the current implementation, a platform which has more than 1 variant with different revisions of a processor has no runtime mechanism available for it to specify which errata workarounds should be enabled or not. -The value of the build flags are 0 by default, that is, disabled. Any other -value will enable it. +The value of the build flags is 0 by default, that is, disabled. A value of 1 +will enable it. -For Cortex-A53, following errata build flags are defined : +For Cortex-A53, the following errata build flags are defined : - ``ERRATA_A53_826319``: This applies errata 826319 workaround to Cortex-A53 CPU. This needs to be enabled only for revision <= r0p2 of the CPU. @@ -97,7 +97,7 @@ For Cortex-A53, following errata build flags are defined : Earlier revisions of the CPU have other errata which require the same workaround in software, so they should be covered anyway. -For Cortex-A57, following errata build flags are defined : +For Cortex-A57, the following errata build flags are defined : - ``ERRATA_A57_806969``: This applies errata 806969 workaround to Cortex-A57 CPU. This needs to be enabled only for revision r0p0 of the CPU. @@ -127,11 +127,33 @@ For Cortex-A57, following errata build flags are defined : CPU. This needs to be enabled only for revision <= r1p3 of the CPU. -For Cortex-A72, following errata build flags are defined : +For Cortex-A72, the following errata build flags are defined : - ``ERRATA_A72_859971``: This applies errata 859971 workaround to Cortex-A72 CPU. This needs to be enabled only for revision <= r0p3 of the CPU. +DSU Errata Workarounds +---------------------- + +Similar to CPU errata, TF-A also implements workarounds for DSU (DynamIQ +Shared Unit) errata. The DSU errata details can be found in the respective Arm +documentation: + +- `Arm DSU Software Developers Errata Notice`_. + +Each erratum is identified by an ``ID``, as defined in the DSU errata notice +document. Thus, the build flags which enable/disable the errata workarounds +have the format ``ERRATA_DSU_<ID>``. The implementation and application logic +of DSU errata workarounds are similar to `CPU errata workarounds`_. + +For DSU errata, the following build flags are defined: + +- ``ERRATA_DSU_936184``: This applies errata 936184 workaround for the + affected DSU configurations. This errata applies only for those DSUs that + contain the ACP interface **and** the DSU revision is older than r2p0 (on + r2p0 it is fixed). However, please note that this workaround results in + increased DSU power consumption on idle. + CPU Specific optimizations -------------------------- @@ -171,3 +193,4 @@ architecture that can be enabled by the platform as desired. .. _Cortex-A72 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm012079/index.html .. _Firmware Design guide: firmware-design.rst .. _Cortex-A57 Software Optimization Guide: http://infocenter.arm.com/help/topic/com.arm.doc.uan0015b/Cortex_A57_Software_Optimization_Guide_external.pdf +.. _Arm DSU Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm138168/index.html
\ No newline at end of file diff --git a/docs/user-guide.rst b/docs/user-guide.rst index 2ef7c61d..3f8170fd 100644 --- a/docs/user-guide.rst +++ b/docs/user-guide.rst @@ -67,8 +67,9 @@ Compiler 6. See instructions below on how to switch the default compiler. In addition, the following optional packages and tools may be needed: -- ``device-tree-compiler`` package if you need to rebuild the Flattened Device - Tree (FDT) source files (``.dts`` files) provided with this software. +- ``device-tree-compiler`` (dtc) package if you need to rebuild the Flattened Device + Tree (FDT) source files (``.dts`` files) provided with this software. The + version of dtc must be 1.4.6 or above. - For debugging, Arm `Development Studio 5 (DS-5)`_. diff --git a/include/lib/cpus/aarch64/dsu_def.h b/include/lib/cpus/aarch64/dsu_def.h new file mode 100644 index 00000000..0e2d93a8 --- /dev/null +++ b/include/lib/cpus/aarch64/dsu_def.h @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef DSU_DEF_H +#define DSU_DEF_H + +#include <utils_def.h> + +/******************************************************************** + * DSU control registers definitions * + ********************************************************************/ +#define CLUSTERCFR_EL1 S3_0_C15_C3_0 +#define CLUSTERIDR_EL1 S3_0_C15_C3_1 +#define CLUSTERACTLR_EL1 S3_0_C15_C3_3 + +/******************************************************************** + * DSU control registers bit fields * + ********************************************************************/ +#define CLUSTERIDR_REV_SHIFT U(0) +#define CLUSTERIDR_REV_BITS U(4) +#define CLUSTERIDR_VAR_SHIFT U(4) +#define CLUSTERIDR_VAR_BITS U(4) +#define CLUSTERCFR_ACP_SHIFT U(11) + +/******************************************************************** + * Masks applied for DSU errata workarounds * + ********************************************************************/ +#define DSU_ERRATA_936184_MASK (ULL(0x3) << 15) + +#endif /* DSU_DEF_H */ diff --git a/lib/cpus/aarch64/cortex_a55.S b/lib/cpus/aarch64/cortex_a55.S index 741c7734..4e9bd9f6 100644 --- a/lib/cpus/aarch64/cortex_a55.S +++ b/lib/cpus/aarch64/cortex_a55.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -11,6 +11,14 @@ #include <cpu_macros.S> #include <plat_macros.S> +func cortex_a55_reset_func + mov x19, x30 +#if ERRATA_DSU_936184 + bl errata_dsu_936184_wa +#endif + ret x19 +endfunc cortex_a55_reset_func + /* --------------------------------------------- * HW will do the cache maintenance while powering down * --------------------------------------------- @@ -27,6 +35,26 @@ func cortex_a55_core_pwr_dwn ret endfunc cortex_a55_core_pwr_dwn +#if REPORT_ERRATA +/* + * Errata printing function for Cortex A55. Must follow AAPCS & can use stack. + */ +func cortex_a55_errata_report + stp x8, x30, [sp, #-16]! + bl cpu_get_rev_var + mov x8, x0 + + /* + * Report all errata. The revision variant information is at x8, where + * "report_errata" is expecting it and it doesn't corrupt it. + */ + report_errata ERRATA_DSU_936184, cortex_a55, dsu_936184 + + ldp x8, x30, [sp], #16 + ret +endfunc cortex_a55_errata_report +#endif + /* --------------------------------------------- * This function provides cortex_a55 specific * register information for crash reporting. @@ -47,5 +75,5 @@ func cortex_a55_cpu_reg_dump endfunc cortex_a55_cpu_reg_dump declare_cpu_ops cortex_a55, CORTEX_A55_MIDR, \ - CPU_NO_RESET_FUNC, \ + cortex_a55_reset_func, \ cortex_a55_core_pwr_dwn diff --git a/lib/cpus/aarch64/cortex_a75.S b/lib/cpus/aarch64/cortex_a75.S index 73f566f4..e121b7da 100644 --- a/lib/cpus/aarch64/cortex_a75.S +++ b/lib/cpus/aarch64/cortex_a75.S @@ -11,6 +11,7 @@ #include <cpu_macros.S> func cortex_a75_reset_func + mov x19, x30 #if IMAGE_BL31 && WORKAROUND_CVE_2017_5715 cpu_check_csv2 x0, 1f adr x0, wa_cve_2017_5715_bpiall_vbar @@ -26,6 +27,10 @@ func cortex_a75_reset_func isb #endif +#if ERRATA_DSU_936184 + bl errata_dsu_936184_wa +#endif + #if ENABLE_AMU /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ mrs x0, actlr_el3 @@ -49,7 +54,7 @@ func cortex_a75_reset_func msr CPUAMCNTENSET_EL0, x0 isb #endif - ret + ret x19 endfunc cortex_a75_reset_func func check_errata_cve_2017_5715 @@ -106,6 +111,7 @@ func cortex_a75_errata_report */ report_errata WORKAROUND_CVE_2017_5715, cortex_a75, cve_2017_5715 report_errata WORKAROUND_CVE_2018_3639, cortex_a75, cve_2018_3639 + report_errata ERRATA_DSU_936184, cortex_a75, dsu_936184 ldp x8, x30, [sp], #16 ret diff --git a/lib/cpus/aarch64/cortex_a76.S b/lib/cpus/aarch64/cortex_a76.S index 51d0b15e..1697c55d 100644 --- a/lib/cpus/aarch64/cortex_a76.S +++ b/lib/cpus/aarch64/cortex_a76.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -207,6 +207,7 @@ func cortex_a76_disable_wa_cve_2018_3639 endfunc cortex_a76_disable_wa_cve_2018_3639 func cortex_a76_reset_func + mov x19, x30 #if WORKAROUND_CVE_2018_3639 mrs x0, CORTEX_A76_CPUACTLR2_EL1 orr x0, x0, #CORTEX_A76_CPUACTLR2_EL1_DISABLE_LOAD_PASS_STORE @@ -224,7 +225,11 @@ func cortex_a76_reset_func msr vbar_el3, x0 isb #endif - ret + +#if ERRATA_DSU_936184 + bl errata_dsu_936184_wa +#endif + ret x19 endfunc cortex_a76_reset_func /* --------------------------------------------- @@ -258,6 +263,7 @@ func cortex_a76_errata_report * checking functions of each errata. */ report_errata WORKAROUND_CVE_2018_3639, cortex_a76, cve_2018_3639 + report_errata ERRATA_DSU_936184, cortex_a76, dsu_936184 ldp x8, x30, [sp], #16 ret diff --git a/lib/cpus/aarch64/denver.S b/lib/cpus/aarch64/denver.S index f04dbd6c..a981d02c 100644 --- a/lib/cpus/aarch64/denver.S +++ b/lib/cpus/aarch64/denver.S @@ -189,6 +189,25 @@ func denver_disable_dco ret endfunc denver_disable_dco +func check_errata_cve_2017_5715 + mov x0, #ERRATA_MISSING +#if WORKAROUND_CVE_2017_5715 + /* + * Check if the CPU supports the special instruction + * required to flush the indirect branch predictor and + * RSB. Support for this operation can be determined by + * comparing bits 19:16 of ID_AFR0_EL1 with 0b0001. + */ + mrs x1, id_afr0_el1 + mov x2, #0x10000 + and x1, x1, x2 + cbz x1, 1f + mov x0, #ERRATA_APPLIES +1: +#endif + ret +endfunc check_errata_cve_2017_5715 + /* ------------------------------------------------- * The CPU Ops reset function for Denver. * ------------------------------------------------- @@ -248,6 +267,27 @@ func denver_cluster_pwr_dwn ret endfunc denver_cluster_pwr_dwn +#if REPORT_ERRATA + /* + * Errata printing function for Denver. Must follow AAPCS. + */ +func denver_errata_report + stp x8, x30, [sp, #-16]! + + bl cpu_get_rev_var + mov x8, x0 + + /* + * Report all errata. The revision-variant information is passed to + * checking functions of each errata. + */ + report_errata WORKAROUND_CVE_2017_5715, denver, cve_2017_5715 + + ldp x8, x30, [sp], #16 + ret +endfunc denver_errata_report +#endif + /* --------------------------------------------- * This function provides Denver specific * register information for crash reporting. @@ -267,27 +307,37 @@ func denver_cpu_reg_dump ret endfunc denver_cpu_reg_dump -declare_cpu_ops denver, DENVER_MIDR_PN0, \ +declare_cpu_ops_wa denver, DENVER_MIDR_PN0, \ denver_reset_func, \ + check_errata_cve_2017_5715, \ + CPU_NO_EXTRA2_FUNC, \ denver_core_pwr_dwn, \ denver_cluster_pwr_dwn -declare_cpu_ops denver, DENVER_MIDR_PN1, \ +declare_cpu_ops_wa denver, DENVER_MIDR_PN1, \ denver_reset_func, \ + check_errata_cve_2017_5715, \ + CPU_NO_EXTRA2_FUNC, \ denver_core_pwr_dwn, \ denver_cluster_pwr_dwn -declare_cpu_ops denver, DENVER_MIDR_PN2, \ +declare_cpu_ops_wa denver, DENVER_MIDR_PN2, \ denver_reset_func, \ + check_errata_cve_2017_5715, \ + CPU_NO_EXTRA2_FUNC, \ denver_core_pwr_dwn, \ denver_cluster_pwr_dwn -declare_cpu_ops denver, DENVER_MIDR_PN3, \ +declare_cpu_ops_wa denver, DENVER_MIDR_PN3, \ denver_reset_func, \ + check_errata_cve_2017_5715, \ + CPU_NO_EXTRA2_FUNC, \ denver_core_pwr_dwn, \ denver_cluster_pwr_dwn -declare_cpu_ops denver, DENVER_MIDR_PN4, \ +declare_cpu_ops_wa denver, DENVER_MIDR_PN4, \ denver_reset_func, \ + check_errata_cve_2017_5715, \ + CPU_NO_EXTRA2_FUNC, \ denver_core_pwr_dwn, \ denver_cluster_pwr_dwn diff --git a/lib/cpus/aarch64/dsu_helpers.S b/lib/cpus/aarch64/dsu_helpers.S new file mode 100644 index 00000000..293ed24b --- /dev/null +++ b/lib/cpus/aarch64/dsu_helpers.S @@ -0,0 +1,60 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <asm_macros.S> +#include <dsu_def.h> +#include <errata_report.h> + +/* + * DSU erratum 936184 + * Check the DSU variant, revision and configuration to determine if the + * erratum applies. This erratum was fixed in r2p0. + * + * This function is called from both assembly and C environment. So it + * follows AAPCS. + * + * Clobbers: x0-x3 + */ + .globl check_errata_dsu_936184 + .globl errata_dsu_936184_wa + +func check_errata_dsu_936184 + mov x2, #ERRATA_NOT_APPLIES + mov x3, #ERRATA_APPLIES + + /* Erratum applies only if ACP interface is present in DSU */ + mov x0, x2 + mrs x1, CLUSTERCFR_EL1 + ubfx x1, x1, #CLUSTERCFR_ACP_SHIFT, #1 + cbz x1, 1f + + /* If ACP is present, check if DSU is older than r2p0 */ + mrs x1, CLUSTERIDR_EL1 + + /* DSU variant and revision bitfields in CLUSTERIDR are adjacent */ + ubfx x0, x1, #CLUSTERIDR_REV_SHIFT,\ + #(CLUSTERIDR_REV_BITS + CLUSTERIDR_VAR_BITS) + mov x1, #(0x2 << CLUSTERIDR_REV_BITS) + cmp x0, x1 + csel x0, x2, x3, hs +1: + ret +endfunc check_errata_dsu_936184 + +func errata_dsu_936184_wa + mov x20, x30 + bl check_errata_dsu_936184 + cbz x0, 1f + + /* If erratum applies, we set a mask to a DSU control register */ + mrs x0, CLUSTERACTLR_EL1 + ldr x1, =DSU_ERRATA_936184_MASK + orr x0, x0, x1 + msr CLUSTERACTLR_EL1, x0 + isb +1: + ret x20 +endfunc errata_dsu_936184_wa diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index 456e3e52..40a8ac7c 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -123,6 +123,11 @@ ERRATA_A72_859971 ?=0 # only to r0p0 and r1p0 of the Ares cpu. ERRATA_ARES_1043202 ?=1 +# Flag to apply DSU erratum 936184. This erratum applies to DSUs containing +# the ACP interface and revision < r2p0. Applying the workaround results in +# higher DSU power consumption on idle. +ERRATA_DSU_936184 ?=0 + # Process ERRATA_A53_826319 flag $(eval $(call assert_boolean,ERRATA_A53_826319)) $(eval $(call add_define,ERRATA_A53_826319)) @@ -187,6 +192,10 @@ $(eval $(call add_define,ERRATA_A72_859971)) $(eval $(call assert_boolean,ERRATA_ARES_1043202)) $(eval $(call add_define,ERRATA_ARES_1043202)) +# Process ERRATA_DSU_936184 flag +$(eval $(call assert_boolean,ERRATA_DSU_936184)) +$(eval $(call add_define,ERRATA_DSU_936184)) + # Errata build flags ifneq (${ERRATA_A53_843419},0) TF_LDFLAGS_aarch64 += --fix-cortex-a53-843419 diff --git a/plat/arm/board/common/board_common.mk b/plat/arm/board/common/board_common.mk index d63ae9a3..af47c0de 100644 --- a/plat/arm/board/common/board_common.mk +++ b/plat/arm/board/common/board_common.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -12,13 +12,7 @@ PLAT_BL_COMMON_SOURCES += drivers/arm/pl011/${ARCH}/pl011_console.S \ BL1_SOURCES += plat/arm/board/common/drivers/norflash/norflash.c -BL2_SOURCES += lib/utils/mem_region.c \ - plat/arm/common/arm_nor_psci_mem_protect.c \ - plat/arm/board/common/drivers/norflash/norflash.c - -BL31_SOURCES += lib/utils/mem_region.c \ - plat/arm/board/common/drivers/norflash/norflash.c \ - plat/arm/common/arm_nor_psci_mem_protect.c +BL2_SOURCES += plat/arm/board/common/drivers/norflash/norflash.c ifneq (${TRUSTED_BOARD_BOOT},0) ifneq (${ARM_CRYPTOCELL_INTEG}, 1) diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk index 2b1e0ac7..fd93b997 100644 --- a/plat/arm/board/fvp/platform.mk +++ b/plat/arm/board/fvp/platform.mk @@ -134,13 +134,17 @@ BL1_SOURCES += drivers/io/io_semihosting.c \ BL2_SOURCES += drivers/io/io_semihosting.c \ + lib/utils/mem_region.c \ lib/semihosting/semihosting.c \ lib/semihosting/${ARCH}/semihosting_call.S \ plat/arm/board/fvp/fvp_bl2_setup.c \ plat/arm/board/fvp/fvp_io_storage.c \ plat/arm/board/fvp/fvp_trusted_boot.c \ + plat/arm/common/arm_nor_psci_mem_protect.c \ ${FVP_SECURITY_SOURCES} + + ifeq (${BL2_AT_EL3},1) BL2_SOURCES += plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ plat/arm/board/fvp/fvp_bl2_el3_setup.c \ @@ -156,11 +160,14 @@ BL2U_SOURCES += plat/arm/board/fvp/fvp_bl2u_setup.c \ ${FVP_SECURITY_SOURCES} BL31_SOURCES += drivers/arm/smmu/smmu_v3.c \ + lib/utils/mem_region.c \ plat/arm/board/fvp/fvp_bl31_setup.c \ plat/arm/board/fvp/fvp_pm.c \ plat/arm/board/fvp/fvp_topology.c \ plat/arm/board/fvp/aarch64/fvp_helpers.S \ plat/arm/board/fvp/drivers/pwrc/fvp_pwrc.c \ + plat/arm/board/common/drivers/norflash/norflash.c \ + plat/arm/common/arm_nor_psci_mem_protect.c \ ${FVP_CPU_LIBS} \ ${FVP_GIC_SOURCES} \ ${FVP_INTERCONNECT_SOURCES} \ diff --git a/plat/arm/board/juno/platform.mk b/plat/arm/board/juno/platform.mk index 3ab99ef3..16390fa4 100644 --- a/plat/arm/board/juno/platform.mk +++ b/plat/arm/board/juno/platform.mk @@ -59,7 +59,9 @@ BL1_SOURCES += lib/cpus/aarch64/cortex_a53.S \ ${JUNO_INTERCONNECT_SOURCES} \ ${JUNO_SECURITY_SOURCES} -BL2_SOURCES += plat/arm/board/juno/juno_bl2_setup.c \ +BL2_SOURCES += lib/utils/mem_region.c \ + plat/arm/board/juno/juno_bl2_setup.c \ + plat/arm/common/arm_nor_psci_mem_protect.c \ ${JUNO_SECURITY_SOURCES} BL2U_SOURCES += ${JUNO_SECURITY_SOURCES} @@ -67,7 +69,10 @@ BL2U_SOURCES += ${JUNO_SECURITY_SOURCES} BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \ lib/cpus/aarch64/cortex_a57.S \ lib/cpus/aarch64/cortex_a72.S \ + lib/utils/mem_region.c \ plat/arm/board/juno/juno_topology.c \ + plat/arm/board/common/drivers/norflash/norflash.c \ + plat/arm/common/arm_nor_psci_mem_protect.c \ ${JUNO_GIC_SOURCES} \ ${JUNO_INTERCONNECT_SOURCES} \ ${JUNO_SECURITY_SOURCES} diff --git a/plat/arm/board/sgi575/platform.mk b/plat/arm/board/sgi575/platform.mk index 9893ba50..284bae8a 100644 --- a/plat/arm/board/sgi575/platform.mk +++ b/plat/arm/board/sgi575/platform.mk @@ -5,3 +5,10 @@ # include plat/arm/css/sgi/sgi-common.mk + +BL2_SOURCES += lib/utils/mem_region.c \ + plat/arm/common/arm_nor_psci_mem_protect.c + +BL31_SOURCES += lib/utils/mem_region.c \ + plat/arm/board/common/drivers/norflash/norflash.c \ + plat/arm/common/arm_nor_psci_mem_protect.c diff --git a/plat/arm/board/sgm775/platform.mk b/plat/arm/board/sgm775/platform.mk index 71e71e1c..633cee66 100644 --- a/plat/arm/board/sgm775/platform.mk +++ b/plat/arm/board/sgm775/platform.mk @@ -11,3 +11,10 @@ SGM775_BASE= plat/arm/board/sgm775 FDT_SOURCES += ${SGM775_BASE}/fdts/sgm775_tb_fw_config.dts PLAT_INCLUDES +=-I${SGM775_BASE}/include/ + +BL2_SOURCES += lib/utils/mem_region.c \ + plat/arm/common/arm_nor_psci_mem_protect.c + +BL31_SOURCES += lib/utils/mem_region.c \ + plat/arm/board/common/drivers/norflash/norflash.c \ + plat/arm/common/arm_nor_psci_mem_protect.c diff --git a/plat/rockchip/common/aarch64/plat_helpers.S b/plat/rockchip/common/aarch64/plat_helpers.S index f415f877..f0136b0d 100644 --- a/plat/rockchip/common/aarch64/plat_helpers.S +++ b/plat/rockchip/common/aarch64/plat_helpers.S @@ -18,7 +18,7 @@ .globl platform_cpu_warmboot .globl plat_secondary_cold_boot_setup .globl plat_report_exception - .globl platform_is_primary_cpu + .globl plat_is_my_cpu_primary .globl plat_my_core_pos .globl plat_reset_handler .globl plat_panic_handler @@ -73,12 +73,13 @@ cb_panic: b cb_panic endfunc plat_secondary_cold_boot_setup -func platform_is_primary_cpu +func plat_is_my_cpu_primary + mrs x0, mpidr_el1 and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) cmp x0, #PLAT_RK_PRIMARY_CPU cset x0, eq ret -endfunc platform_is_primary_cpu +endfunc plat_is_my_cpu_primary /* -------------------------------------------------------------------- * void plat_panic_handler(void) diff --git a/plat/rpi3/include/platform_def.h b/plat/rpi3/include/platform_def.h index 19503760..76a5ff44 100644 --- a/plat/rpi3/include/platform_def.h +++ b/plat/rpi3/include/platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -215,7 +215,8 @@ /* * Other memory-related defines. */ -#define ADDR_SPACE_SIZE (ULL(1) << 32) +#define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 32) +#define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 32) #define MAX_MMAP_REGIONS 8 #define MAX_XLAT_TABLES 4 diff --git a/plat/rpi3/platform.mk b/plat/rpi3/platform.mk index 55201eff..d6d0d56c 100644 --- a/plat/rpi3/platform.mk +++ b/plat/rpi3/platform.mk @@ -33,7 +33,7 @@ BL2_SOURCES += common/desc_image_load.c \ plat/rpi3/rpi3_io_storage.c BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \ - plat/common/aarch64/plat_psci_common.c \ + plat/common/plat_psci_common.c \ plat/rpi3/aarch64/plat_helpers.S \ plat/rpi3/rpi3_bl31_setup.c \ plat/rpi3/rpi3_pm.c \ diff --git a/plat/rpi3/rpi3_bl2_setup.c b/plat/rpi3/rpi3_bl2_setup.c index 13e8c015..c78024ea 100644 --- a/plat/rpi3/rpi3_bl2_setup.c +++ b/plat/rpi3/rpi3_bl2_setup.c @@ -24,8 +24,12 @@ static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); * in x0. This memory layout is sitting at the base of the free trusted SRAM. * Copy it to a safe location before its reclaimed by later BL2 functionality. ******************************************************************************/ -void bl2_early_platform_setup(meminfo_t *mem_layout) + +void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, + u_register_t arg2, u_register_t arg3) { + meminfo_t *mem_layout = (meminfo_t *) arg1; + /* Initialize the console to provide early debug support */ rpi3_console_init(); diff --git a/plat/rpi3/rpi3_bl31_setup.c b/plat/rpi3/rpi3_bl31_setup.c index 5bbb13c8..306f26b3 100644 --- a/plat/rpi3/rpi3_bl31_setup.c +++ b/plat/rpi3/rpi3_bl31_setup.c @@ -53,23 +53,21 @@ entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) * tables. BL2 has flushed this information to memory, so we are guaranteed * to pick up good data. ******************************************************************************/ -void bl31_early_platform_setup(void *from_bl2, - void *plat_params_from_bl2) +void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, + u_register_t arg2, u_register_t arg3) + { /* Initialize the console to provide early debug support */ rpi3_console_init(); /* - * In debug builds, we pass a special value in 'plat_params_from_bl2' - * to verify platform parameters from BL2 to BL31. - * In release builds, it's not used. + * In debug builds, a special value is passed in 'arg1' to verify + * platform parameters from BL2 to BL31. Not used in release builds. */ - assert(((uintptr_t)plat_params_from_bl2) == RPI3_BL31_PLAT_PARAM_VAL); + assert(arg1 == RPI3_BL31_PLAT_PARAM_VAL); - /* - * Check params passed from BL2 should not be NULL, - */ - bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2; + /* Check that params passed from BL2 are not NULL. */ + bl_params_t *params_from_bl2 = (bl_params_t *) arg0; assert(params_from_bl2 != NULL); assert(params_from_bl2->h.type == PARAM_BL_PARAMS); |