diff options
Diffstat (limited to 'bl2')
-rw-r--r-- | bl2/aarch32/bl2_entrypoint.S | 7 | ||||
-rw-r--r-- | bl2/aarch64/bl2_entrypoint.S | 4 |
2 files changed, 7 insertions, 4 deletions
diff --git a/bl2/aarch32/bl2_entrypoint.S b/bl2/aarch32/bl2_entrypoint.S index 23d15135..102fd2f5 100644 --- a/bl2/aarch32/bl2_entrypoint.S +++ b/bl2/aarch32/bl2_entrypoint.S @@ -42,12 +42,13 @@ func bl2_entrypoint stcopr r0, VBAR isb - /* ----------------------------------------------------- - * Enable the instruction cache - * ----------------------------------------------------- + /* -------------------------------------------------------- + * Enable the instruction cache - disable speculative loads + * -------------------------------------------------------- */ ldcopr r0, SCTLR orr r0, r0, #SCTLR_I_BIT + bic r0, r0, #SCTLR_DSSBS_BIT stcopr r0, SCTLR isb diff --git a/bl2/aarch64/bl2_entrypoint.S b/bl2/aarch64/bl2_entrypoint.S index 611b8076..c820cd13 100644 --- a/bl2/aarch64/bl2_entrypoint.S +++ b/bl2/aarch64/bl2_entrypoint.S @@ -41,12 +41,14 @@ func bl2_entrypoint /* --------------------------------------------- * Enable the instruction cache, stack pointer - * and data access alignment checks + * and data access alignment checks and disable + * speculative loads. * --------------------------------------------- */ mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT) mrs x0, sctlr_el1 orr x0, x0, x1 + bic x0, x0, #SCTLR_DSSBS_BIT msr sctlr_el1, x0 isb |