diff options
Diffstat (limited to 'docs')
| -rw-r--r-- | docs/cpu-specific-build-macros.md | 2 | ||||
| -rw-r--r-- | docs/plat/nvidia-tegra.md | 23 |
2 files changed, 24 insertions, 1 deletions
diff --git a/docs/cpu-specific-build-macros.md b/docs/cpu-specific-build-macros.md index a743487f..bd7d4ed3 100644 --- a/docs/cpu-specific-build-macros.md +++ b/docs/cpu-specific-build-macros.md @@ -58,7 +58,7 @@ For Cortex-A53, following errata build flags are defined : * `ERRATA_A53_836870`: This applies errata 836870 workaround to Cortex-A53 CPU. This needs to be enabled only for revision <= r0p3 of the CPU. From - r0p4 and onwards, this errata is enabled by default. + r0p4 and onwards, this errata is enabled by default in hardware. For Cortex-A57, following errata build flags are defined : diff --git a/docs/plat/nvidia-tegra.md b/docs/plat/nvidia-tegra.md index b29532c9..b45fec6e 100644 --- a/docs/plat/nvidia-tegra.md +++ b/docs/plat/nvidia-tegra.md @@ -62,9 +62,32 @@ TARGET_SOC=<target-soc e.g. t210|t132> SPD=<dispatcher e.g. tlkd> bl31' Platforms wanting to use different TZDRAM_BASE, can add 'TZDRAM_BASE=<value>' to the build command line. +The Tegra platform code expects a pointer to the following platform specific +structure via 'x1' register from the BL2 layer which is used by the +bl31_early_platform_setup() handler to extract the TZDRAM carveout base and +size for loading the Trusted OS and the UART port ID to be used. The Tegra +memory controller driver programs this base/size in order to restrict NS +accesses. + +typedef struct plat_params_from_bl2 { + /* TZ memory size */ + uint64_t tzdram_size; + /* TZ memory base */ + uint64_t tzdram_base; + /* UART port ID */ + int uart_id; +} plat_params_from_bl2_t; + Power Management ================ The PSCI implementation expects each platform to expose the 'power state' parameter to be used during the 'SYSTEM SUSPEND' call. The state-id field is implementation defined on Tegra SoCs and is preferably defined by tegra_def.h. + +Tegra configs +============= + +* 'tegra_enable_l2_ecc_parity_prot': This flag enables the L2 ECC and Parity + Protection bit, for ARM Cortex-A57 CPUs, during CPU boot. This flag will + be enabled by Tegrs SoCs during 'Cluster power up' or 'System Suspend' exit. |