diff options
Diffstat (limited to 'plat/allwinner')
| -rw-r--r-- | plat/allwinner/sun50i_a64/sunxi_power.c | 13 |
1 files changed, 11 insertions, 2 deletions
diff --git a/plat/allwinner/sun50i_a64/sunxi_power.c b/plat/allwinner/sun50i_a64/sunxi_power.c index 9a273399..af304773 100644 --- a/plat/allwinner/sun50i_a64/sunxi_power.c +++ b/plat/allwinner/sun50i_a64/sunxi_power.c @@ -217,6 +217,7 @@ static int setup_regulator(const void *fdt, int node, static void setup_axp803_rails(const void *fdt) { int node; + bool dc1sw = false; /* locate the PMIC DT node, bail out if not found */ node = fdt_node_offset_by_compatible(fdt, -1, "x-powers,axp803"); @@ -252,11 +253,19 @@ static void setup_axp803_rails(const void *fdt) } if (!strncmp(name, "dc1sw", length)) { - INFO("PMIC: AXP803: Enabling DC1SW\n"); - axp_setbits(0x12, BIT(7)); + /* Delay DC1SW enablement to avoid overheating. */ + dc1sw = true; continue; } } + /* + * If DLDO2 is enabled after DC1SW, the PMIC overheats and shuts + * down. So always enable DC1SW as the very last regulator. + */ + if (dc1sw) { + INFO("PMIC: AXP803: Enabling DC1SW\n"); + axp_setbits(0x12, BIT(7)); + } } int sunxi_pmic_setup(uint16_t socid, const void *fdt) |