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Diffstat (limited to 'plat/hisilicon/hikey960/hikey960_bl2_setup.c')
-rw-r--r--plat/hisilicon/hikey960/hikey960_bl2_setup.c29
1 files changed, 5 insertions, 24 deletions
diff --git a/plat/hisilicon/hikey960/hikey960_bl2_setup.c b/plat/hisilicon/hikey960/hikey960_bl2_setup.c
index 788392db..7102de85 100644
--- a/plat/hisilicon/hikey960/hikey960_bl2_setup.c
+++ b/plat/hisilicon/hikey960/hikey960_bl2_setup.c
@@ -28,26 +28,7 @@
#include "hikey960_def.h"
#include "hikey960_private.h"
-/*
- * The next 2 constants identify the extents of the code & RO data region.
- * These addresses are used by the MMU setup code and therefore they must be
- * page-aligned. It is the responsibility of the linker script to ensure that
- * __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses.
- */
-#define BL2_RO_BASE (unsigned long)(&__RO_START__)
-#define BL2_RO_LIMIT (unsigned long)(&__RO_END__)
-
-#define BL2_RW_BASE (BL2_RO_LIMIT)
-
-/*
- * The next 2 constants identify the extents of the coherent memory region.
- * These addresses are used by the MMU setup code and therefore they must be
- * page-aligned. It is the responsibility of the linker script to ensure that
- * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to
- * page-aligned addresses.
- */
-#define BL2_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
-#define BL2_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
+#define BL2_RW_BASE (BL_CODE_END)
static meminfo_t bl2_el3_tzram_layout;
static console_pl011_t console;
@@ -312,10 +293,10 @@ void bl2_el3_plat_arch_setup(void)
{
hikey960_init_mmu_el3(bl2_el3_tzram_layout.total_base,
bl2_el3_tzram_layout.total_size,
- BL2_RO_BASE,
- BL2_RO_LIMIT,
- BL2_COHERENT_RAM_BASE,
- BL2_COHERENT_RAM_LIMIT);
+ BL_CODE_BASE,
+ BL_CODE_END,
+ BL_COHERENT_RAM_BASE,
+ BL_COHERENT_RAM_END);
}
void bl2_platform_setup(void)