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Add a new SIP call FSL_SIP_BUILDINFO to return the current commit id
in 7 hexadecimal digits which are parsed from the version_string.
Signed-off-by: Ye Li <ye.li@nxp.com>
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Fix below build error on i.MX8QXP when using poky
tool chain:
CC plat/freescale/common/cpufreq.c
plat/freescale/common/cpufreq.c:27:18:
error: "ap_cluster_index" defined but not used
[-Werror=unused-const-variable=]
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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Add system_off pcsi callback to avoid below kernel
message when doing power off:
[11613.953711] reboot: Power down
[11613.958318] systemd-shutdow: 8 output lines suppressed due to ratelimiting
[11613.965285] Kernel panic - not syncing: Attempted to kill init! exitcode=0x00
[11613.965285]
[11613.974441] CPU: 0 PID: 1 Comm: systemd-shutdow Not tainted 4.9.11-03354-g0e1
[11613.982369] Hardware name: Freescale i.MX8QXP LPDDR4 ARM2 (DT)
[11613.988216] Call trace:
[11613.990681] [<ffff0000080882bc>] dump_backtrace+0x0/0x1a8
[11613.996092] [<ffff000008088478>] show_stack+0x14/0x1c
[11614.001154] [<ffff0000083aaf98>] dump_stack+0x8c/0xac
[11614.006213] [<ffff000008162aac>] panic+0x124/0x28c
[11614.011016] [<ffff0000080c0b20>] complete_and_exit+0x0/0x20
[11614.016600] [<ffff0000080dc6d8>] SyS_reboot+0x168/0x244
[11614.021829] [<ffff000008082ef0>] el0_svc_naked+0x24/0x28
[11614.027153] Kernel Offset: disabled
[11614.030646] Memory Limit: none
[11614.040755] ---[ end Kernel panic - not syncing: Attempted to kill init! exi0
[11614.040755]
As there is no system power off SCFW API available now, so just
simply do wfi and never return when system_off is called.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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The GPC_CPU_PGC_SW_PDN_REQ offset should be 0xfc, previous
offset is incorrect, so actually ARM core is NOT powered
down and the power leakage is very high.
With this fix, each ARM core's leakage is about 25mA@0.9V.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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Add SRTC SIP support for i.MX8QM/i.MX8QXP.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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Add SCFW timer API support.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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Add i.MX8QXP board reset support.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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Add i.MX8QM board reboot support.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@nxp.com>
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The bits[3:0] of CPU_PGC_PUP/PDN_TRG use core's SW
power up/down. prevous bits assignment is wrong, so
fix it.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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Linux kernel will issue cpu-freq scale via SIP, ATF
calls SCFW API to finish the CPU frequency scale.
Move SIP service code from i.mx8mq to common place for
all i.mx SoCs.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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- USB PHY reset bit in SRC needs to be clear before
doing USB PHY power gating in GPC, only needs to
do once;
- Need to handle GPC_PU_PWRHSK during power up/down;
- Enable GPC pu power gate support.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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As there are too many difference between each PU's power
on/off flow, here enable all PUs power until all modules'
power on/off function ready and tested, then we will enable
this PU PGC feature.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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the PCIE1 and PCIE2 share the same reset signal, if PCIE2 is power down,
PCIE1 will also be power down, so when we need to power up PCIE1, the PCIE2
need to power up too, only PCIE1 is power down, the PCIE2 power domain can
be power down too
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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No need to enable all PU power during boot up, module driver
will enable their power domain as needed.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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Set the MPROTx and OPACRx in AIPS4 configuration registers to allow user mode
and non-supervisor privilege level to access.
Signed-off-by: Ye Li <ye.li@nxp.com>
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Reserve the memory region that is only can access by ATF. ATF is running
in this memory region, while masters in other partitions can't access it.
Signed-off-by: Ye Li <ye.li@nxp.com>
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Change to search the ATF owned memory regions and assign them to non-secure
OS partition. Not allocate new memory region for each one.
Signed-off-by: Ye Li <ye.li@nxp.com>
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The power domain id does NOT equal to the register bit
offset, so need to do a mapping here.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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Add hardware power down for all power domains. Make
imx_gpc_set_m_core_pgc usable for all MIX and PU PGC.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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Need to mask all M4 IRQ and override all PLLs/OSC
before entering DSM mode, but due to DRAM self-refresh
NOT ready, non-fast wakeup mode is NOT working, so
we still use fast wakeup mode, which means DSM mode
by default is NOT entered.
After DRAM self-refresh is added, we will switch
to non-fast wakeup mode to make DSM work.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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Move TZC EN into SPL, and add check in ATF.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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Add SNVS mapping to avoid system off failure.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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enable tzc380 for i.mx8mq
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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Add tzc380 support.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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Change back BL31_LIMIT to 0x40020000,
because TZC380 could not support 4K aligned address.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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Add console init
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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Add system off support, linux kernel can issue
"poweroff" to power down system.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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Add wdog reset support.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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Enable the non-privilege access for AIPS address space.
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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Add basic support for i.MX8MQ.
1. SMP support is ok.
2. basic suspend/resume support is ok.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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As we already have control for debug console in platform_def.h,
so no need to un-initialize console in plat runtime setup, just
overwrite the common implementation with blank function.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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Signed-off-by: Nitin Garg <nitin.garg@nxp.com>
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Not only the resources, but also the memory regions need to assign to
non-secure partition. Otherwise, when the boot partition is secured,
the OS non-secure partition can't access any memory.
This patch currently assign all memory to NS partition, since it is not
isolated, the current secure partition also can access them. In future,
may need to change the regions for reserving some memory in secure
partition for ATF and BL32.
Signed-off-by: Ye Li <ye.li@nxp.com>
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Signed-off-by: Nitin Garg <nitin.garg@nxp.com>
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missed bit 31 and 30 which are needed
Signed-off-by: Nitin Garg <nitin.garg@nxp.com>
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Signed-off-by: Nitin Garg <nitin.garg@nxp.com>
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Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@nxp.com>
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Disable ATF console output for iMX8QM
Signed-off-by: Nitin Garg <nitin.garg@nxp.com>
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Disable debug console by default on i.MX8QXP.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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Debug console baudrate should be 115200 for i.MX8QXP real board.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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Add necessary resources to secure partition for protection.
Also add in functionality to allow for register access
of some secure-owned peripherals.
These peripherals will still be protected from power or
clk changes.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Teo Hall <teo.hall@nxp.com>
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Need to add support for booting up A72 cluster only,
so on need to check the cluster ID for primary CPU,
that means if CPU ID is 0, then it can be as primary
CPU.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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Signed-off-by: Nitin Garg <nitin.garg@nxp.com>
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change MMU mapping to use the address of
the MU currently being used for ATF
Signed-off-by: Teo Hall <teo.hall@nxp.com>
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add more resources to secure partition for
protection. Also add in functionality to allow
for register access of some secure-owned
peripherals.
These peripherals will still be protected from
power or clk changes.
Signed-off-by: Teo Hall <teo.hall@nxp.com>
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add rm svc api and set aside separate MU for
secure api calls into SCU
Signed-off-by: Teo Hall <teo.hall@nxp.com>
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add plat_crash_print_regs macro function to
allow building with debug
Signed-off-by: Teo Hall <teo.hall@nxp.com>
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UART baudrate is 115200 on i.MX8QM ARM2 board.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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When secondary CPUs are offline, some platforms do NOT
support shutting down secondary CPUs by themself, need
to use other online CPU to shutdown those CPUs which
are being offline, this patch adds killing offline CPUs.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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